MT8931CP Zarlink Semiconductor, MT8931CP Datasheet - Page 18

• Manufacturer Part Number: MT8931CP
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Note 3: All ST-BUS channels are enabled in controllerless mode.
Note 1: The HDLC receiver must be enabled as well as the designated channel.
18
BIT
BIT
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
RxPrtSel
TxPrtSel
CH3o
CH2o
CH1o
CH0o
CH3i
CH2i
CH1i
CH0i
ADRec
NAME
NAME
HLoop
RxEn
TxEn
IFTF
NA
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel).
If ’0’, then the channel is disabled, and will read FF
If ’1’, then the ST-BUS channel 2 input port is enabled (B1-channel).
If ’0’, then the channel is disabled, and will read FF
If ’1’, then the ST-BUS channel 1 input port is enabled (C-channel).
If ’0’, then the channel is disabled, and will read 00
If ’1’, then the ST-BUS channel 0 input port is enabled (D-channel).
If ’0’, then the channel is disabled, and will read FF
If ’1’, then the ST-BUS channel 3 output port is enabled (B2-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
If ’1’, then the ST-BUS channel 2 output port is enabled (B1-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
If ’1’, then the ST-BUS channel 1 output port is enabled (C-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance
If ’1’, then the ST-BUS channel 0 output port is enabled (D-channel).
If ’0’, then the channel is disabled and it will be placed in High impedance.
Table 5. ST-BUS Control Register (Read/Write Add. 00001
A ’1’ enables the HDLC transmitter for the selected D-channel (i.e., ST-BUS or S-Bus).
A ’0’ disables the HDLC transmitter (i.e., an all 1s signal will be sent).
A ’1’ enables the HDLC receiver for the selected D-channel (i.e., ST-BUS or S-Bus).
A ’0’ disables the HDLC receiver (i.e., an all 1s signal will be received).
If ’1’, then the address recognition is enabled. This forces the receiver to recognize only
those packets having the unique address as programmed in the Receive Address
Registers or if the address byte is the All-Call address (all 1s).
If ’0’, then the address recognition is disabled and every valid packet is stored in the
received FIFO.
This bit selects the port of the HDLC transmitted D-channel.
A’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.
This bit selects the port of the HDLC received D-channel.
A ’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.
This bit selects the Inter Frame Time Fill.
A ’1’ selects continuous flags. A ’0’ selects an all 1’s idle state.
Keep at ’0’ for normal operation.
A ’1’ will activate the HDLC loopback where the transmitted D-channel is looped back to
the received D-channel
TE mode, however, the DReq bit of the C-channel Control Register must be set to ‘1’ for
the packet to be transmitted to the S-Bus.
A ’0’ disables the loopback.
Table 6. HDLC Control Register 1 (Read/Write Add. 00010
(1)
. In NT mode, the transmission of the packet is not affected. In
DESCRIPTION
DESCRIPTION
H
H
H
H
.
.
.
.
B
B
)
)
Data Sheet