MPC9352 Motorola, MPC9352 Datasheet - Page 3

no-image

MPC9352

Manufacturer Part Number
MPC9352
Description
3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Manufacturer
Motorola
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9352AC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9352AC
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MPC9352ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9352FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
TIMING SOLUTIONS
Table 1: PIN CONFIGURATION
CCLK
FB_IN
F_RANGE
FSELA
FSELB
FSELC
PLL_EN
MR/OE
QA0–4, QB0–3, QC0–1
GND
VCCA
VCC
Table 2: FUNCTION TABLE
F_RANGE
PLL_EN
Control
FSELA
FSELB
FSELC
MR/OE
Pin
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
Default
Input
Input
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
Supply
0
0
0
0
0
0
I/O
Freescale Semiconductor, Inc.
VCO ÷ 1 (High input frequency range)
Output divider ÷ 4
Output divider ÷ 4
Output divider ÷ 2
Outputs enabled (active)
Normal operation mode with PLL enabled.
For More Information On This Product,
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
Type
Go to: www.freescale.com
PLL reference clock signal
PLL feedback signal input, connect to an output
PLL frequency range select
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
PLL enable/disable
Output enable/disable (high–impedance tristate) and device reset
Clock outputs
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin V
applications section for details.
Positive power supply for I/O and core
0
3
VCO ÷ 2 (Low input frequency range)
Output divider ÷ 6
Output divider ÷ 2
Output divider ÷ 4
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC9352 requires
reset at power–up and after any loss of PLL
lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length
of the reset pulse should be greater than two
reference clock cycles (CCLK).
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC9352 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
Function
CCA
. Please see
1
MPC9352
MOTOROLA

Related parts for MPC9352