MPC9352 Motorola, MPC9352 Datasheet - Page 8

• Manufacturer Part Number: MPC9352
• Description: 3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
• Manufacturer: Motorola

MPC9352
Programming the MPC9352
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
a.
b.
c.
a.
b.
c.
MOTOROLA
Table 9: MPC9352 Example Configuration (F_RANGE = 0)
Table 10: MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
PLL Feedback
The MPC9352 supports output clock frequencies from
VCO ÷ 12
VCO ÷ 4
VCO ÷ 6
VCO ÷ 8
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
b
c
b
c
fref
fref
33.3-66.67
16.67-33.3
50-100
25-50
a
a
[MHz]
[MHz]
FSELA
FSELA
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
FSELB
FSELB
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
APPLICATIONS INFORMATION
Go to: www.freescale.com
FSELC
FSELC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fref
fref
fref ⋅ 2÷3 (33-66 MHz)
fref ⋅ 2÷3 (33-66 MHz)
fref
fref
fref
fref
fref
fref
fref
fref
fref
fref
fref ⋅2÷3 (16-33 MHz)
fref ⋅2÷3 (16-33 MHz)
QA[0:4]:fref ratio
QA[0:4]:fref ratio
8
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2
as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various
output configurations and frequency ratios supported by the
MPC9352. See also Table 9, Table 10 and Figure 3 to Figure
6 for further reference. A
feedback.
(50-100 MHz)
(50-100 MHz)
(33-66 MHz)
(33-66 MHz)
(33-66 MHz)
(33-66 MHz)
(25-50 MHz)
(25-50 MHz)
(16-33 MHz)
(16-33 MHz)
(16-33 MHz)
(16-33 MHz)
fref
fref
fref
fref
fref
fref
fref
fref
fref ⋅3÷2 (50-100 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅ 3 (50-100 MHz)
QB[0:3]:fref ratio
QB[0:3]:fref ratio
(50-100 MHz)
(50-100 MHz)
(50-100 MHz)
(50-100 MHz)
÷
(25-50 MHz)
(25-50 MHz)
(25-50 MHz)
(25-50 MHz)
2 output divider cannot be used for
fref ⋅ 2 (100-200 MHz)
fref
fref ⋅ 2 (100-200 MHz)
fref
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (50-100 MHz)
fref
fref
fref ⋅ 2 (50-100 MHz)
fref ⋅ 2 (50-100 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅3÷2 (25-50 MHz)
TIMING SOLUTIONS
QC[0:1]:fref ratio
QC[0:1]:fref ratio
(50-100 MHz)
(50-100 MHz)
(25-50 MHz)
(25-50 MHz)