BR24C01 ROHM Electronics, BR24C01 Datasheet - Page 4

• Manufacturer Part Number: BR24C01
• Manufacturer: ROHM Electronics

Memory ICs
! ! ! ! Timing charts
! ! ! ! Circuit operation
(1) Start condition (recognition of start bit)
(2) Stop condition (recognition of stop bit)
(3) Precautions concerning write commands
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from
LOW to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.
(output)
SDA
(input)
SCL
SCL
SDA
SCL
SDA
SDA
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(n address)
Write data
t
SU
: STA
· Data is read on the rising edge of SCL.
· Data is output in synchronization with the falling edge of SCL.
t
HD
t
BUF
D0
:
STA
Fig.1 Synchronized data input / output timing
ACK
START BIT
t
HD
Fig.2 Write cycle timing
: STA
t
R
Stop condition
t
SU
: DAT
t
WR
t
t
t
F
LOW
PD
t
SU
: STO
Start condition
t
HIGH
t
DH
STOP BIT
t
HD
: DAT