BR24C01 ROHM Electronics, BR24C01 Datasheet - Page 6

• Manufacturer Part Number: BR24C01
• Manufacturer: ROHM Electronics

Memory ICs
(7) Byte write cycle
When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW
acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not
sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not
detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop
bit). The IC then enters the waiting or standby state.
(See Fig.3 for acknowledge signal (ACK signal) response.)
BR24C01A-W / AF-W / AFJ-W / AFV-W
LINE
WP
SDA
(µ-COM output data)
R
S
T
A
T
(IC output data)
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
(from µ-COM)
1
SCL
SDA
SDA
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
0
Start condition (start bit)
ADDRESS
1
SLAVE
0 A2 A1 A0
W
W
R
E
R
T
I
/
Fig.3 Acknowledge (ACK signal) response
A
C
K
1
∗
(during write and read slave address input)
WA
6
ADDRESS
WORD
Fig.4
WA
0
Acknowledge signal (ACK signal)
C
A
K
8
D7
DATA
9
D0
C
A
K
O
S
P
T