PIC12CE67 Microchip Technology, PIC12CE67 Datasheet - Page 59

• Manufacturer Part Number: PIC12CE67
• Description: 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: Microchip Technology

FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
9.9
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
9.10
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
9.11
PIC12CE67X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (V
specification). GP1 (clock) becomes the programming
clock and GP0 (data) becomes the programming data.
Both GP0 and GP1 are Schmitt Trigger inputs in this
mode.
Note 1:
1998 Microchip Technology Inc.
Note:
INSTRUCTION FLOW
GPIF flag
(INTCON<0>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT(4)
GPIO pin
2:
3:
4:
OSC1
Program Verification/Code Protection
ID Locations
In-Circuit Serial Programming
PP
PC
XT, HS or LP oscillator mode assumed.
T
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
Microchip does not recommend code pro-
tecting windowed devices.
OST
) pin from V
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
IL
(drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.
to V
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
IHH
(see programming
Q1
Processor in
SLEEP
PC+2
Preliminary
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A 6-
bit command is then supplied to the device. Depending
on the command, 14-bits of program data are then sup-
plied to or from the device, depending if the command
was a load or a read. For complete details of serial pro-
gramming, please refer to the PIC12CE67X Program-
ming Specifications.
FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL
PC+2
External
Connector
Signals
Data I/O
CLK
+5V
V
0V
PP
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
PROGRAMMING
CONNECTION
PIC12CE67X
To Normal
Connections
To Normal
Connections
Q1 Q2 Q3 Q4
Inst(0004h)
Dummy cycle
0004h
DS40181B-page 59
V
V
MCLR/V
GP1
GP0
Q1 Q2 Q3 Q4
DD
SS
PIC12CE67X
Inst(0005h)
Inst(0004h)
0005h
V
PP
DD