PIC16C62B Microchip Technology, PIC16C62B Datasheet
PIC16C62B
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PIC16C62B Summary of contents
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... High Sink/Source Current 25/25 mA • Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < typical standby current 1998 Microchip Technology Inc. PIC16C62B/72A Pin Diagram SDIP, SOIC, SSOP, Windowed CERDIP MCLR/V • RA0/AN0 2 RA1/AN1 ...
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... Analog-to-Digital Module DS35008A-page 2 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT RC7 RC6 RC5/SDO RC4/SDI/SDA PIC16C62B MHz POR, BOR (PWRT, OST) 2K 128 6 Ports A,B SSP — Preliminary PIC16C72A MHz POR, BOR (PWRT, OST) 2K 128 7 Ports A,B,C ...
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... Appendix C: Migration from Base-line to Mid-Range Devices ................................................................................... 104 Index ........................................................................................................................................................................... 105 On-Line Support.......................................................................................................................................................... 109 Reader Response ....................................................................................................................................................... 110 PIC16C62B/72A Product Identification System .......................................................................................................... 111 Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. ...
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... PIC16C62B/72A NOTES: DS35008A-page 4 Preliminary 1998 Microchip Technology Inc. ...
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... Timer0 Timer1 Synchronous CCP1 Serial Port Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C62B. 1998 Microchip Technology Inc. PIC16C62B/72A ommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are two devices (PIC16C62B, PIC16C72A) cov- ered by this datasheet ...
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... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: The A/D module is not available on the PIC16C62B. DS35008A-page 6 I/O/P ...
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... PICmicro Mid-Range Reference Manual, (DS33023). 2.1 Program Memory Organization The PIC16C62B/72A PICmicros have a 13-bit program counter capable of addressing program memory space. Each device has words of pro- gram memory. Accessing a location above the physi- cally implemented address will cause a wraparound. ...
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... Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C62B, read as '0'. Preliminary REGISTER FILE MAP File Address (1) (1) INDF INDF 80h TMR0 OPTION_REG 81h ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1998 Microchip Technology Inc. PIC16C62B/72A It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits from the STATUS register ...
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... PIC16C62B/72A 2.2.2.2 OPTION_REG REGISTER The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 2-4: ...
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... RBIF: RB Port Change Interrupt Flag bit least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state 1998 Microchip Technology Inc. PIC16C62B/72A Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. DS35008A-page 14 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. 1998 Microchip Technology Inc. ...
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... PIC16C62B/72A 2.2.2.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry con- tain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. ...
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... The tenth push overwrites the second push (and so on). 1998 Microchip Technology Inc. PIC16C62B/72A 2.4 Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page ...
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... EXAMPLE 2-2: movlw movwf NEXT clrf incf btfss goto CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-9. However, IRP is not used in the PIC16C62B/72A. 0 IRP (2) bank select 80h 100h 180h not used ...
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... BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'. 1998 Microchip Technology Inc. PIC16C62B/72A FIGURE 3-1: Data bus D WR Port Manual, CK Data Latch D WR TRIS CK TRIS Latch RD PORT ...
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... Bit 7 Bit 6 05h PORTA — — (for PIC16C72A only) 05h PORTA — — (for PIC16C62B only) 85h TRISA — — (1) 9Fh ADCON1 — — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: On PIC16C72A only. ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). 1998 Microchip Technology Inc. PIC16C62B/72A Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin con- fi ...
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... PIC16C62B/72A TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3 bit3 TTL RB4 bit4 TTL RB5 bit5 TTL (2) RB6 bit6 TTL/ST (2) RB7 bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
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... BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 1998 Microchip Technology Inc. PIC16C62B/72A FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) (2) PORT/PERIPHERAL Select Peripheral Data Out 0 Data bus PORT ...
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... PIC16C62B/72A TABLE 3-5 PORTC FUNCTIONS Name Bit# Buffer Type bit0 RC0/T1OSO/T1CKI ST RC1/T1OSI bit1 ST RC2/CCP1 bit2 ST RC3/SCK/SCL bit3 ST RC4/SDI/SDA bit4 ST RC5/SDO bit5 ST RC6 bit6 ST RC7 bit7 ST Legend Schmitt Trigger input TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 ...
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... T0SE T0CS Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram). 1998 Microchip Technology Inc. PIC16C62B/72A Additional information on external clock requirements is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). 4.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer, respectively (Figure 4-2) ...
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... PIC16C62B/72A 4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicro Mid-Range Reference Manual, DS33023) must be executed when chang- ing the prescaler assignment from Timer0 to the WDT ...
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... Internal clock (F /4) OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1998 Microchip Technology Inc. PIC16C62B/72A 5.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON< ...
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... PIC16C62B/72A FIGURE 5-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1 TMR1H T1OSC RC0/T1OSO/T1CKI RC1/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS35008A-page 28 0 TMR1L 1 TMR1ON T1SYNC on/off 1 Prescaler ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. 1998 Microchip Technology Inc. PIC16C62B/72A 5.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt fl ...
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... PIC16C62B/72A NOTES: DS35008A-page 30 Preliminary 1998 Microchip Technology Inc. ...
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... PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. 1998 Microchip Technology Inc. PIC16C62B/72A Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6 simplified block diagram of the Timer2 module ...
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... PIC16C62B/72A 6.1 Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (F /4) has a prescale option of 1:1, OSC 1:4 or 1:16, selected by T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in fl ...
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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 1998 Microchip Technology Inc. PIC16C62B/72A Additional information on the CCP module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). TABLE 7-1 ...
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... PIC16C62B/72A 7.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... CCP1X Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. 1998 Microchip Technology Inc. PIC16C62B/72A 7.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. Note: ...
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... PIC16C62B/72A 7.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... CCPR1H Capture/Compare/PWM register1 (MSB) 17h CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. 1998 Microchip Technology Inc. PIC16C62B/72A 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 0xFF 0xFF 0xFF 10 10 ...
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... PIC16C62B/72A NOTES: DS35008A-page 38 Preliminary 1998 Microchip Technology Inc. ...
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... Inter-Integrated Circuit (I C) For more information on SSP operation (including Overview), refer to the PICmicro™ Mid-Range Ref- erence Manual, (DS33023). Also, refer to Application Note AN578, “Use of the SSP Module in the I Master Environment.” 1998 Microchip Technology Inc. PIC16C62B/72A 2 C Multi- Preliminary DS35008A-page 39 ...
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... PIC16C62B/72A FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 SMP CKE D/A P bit7 bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode ...
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... C firmware controlled master operation (slave idle) 2 1110 = I C slave mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C slave mode, 10-bit address with start and stop bit interrupts enabled 1998 Microchip Technology Inc. PIC16C62B/72A R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 SSPM1 SSPM0 ...
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... PIC16C62B/72A 8.2 SPI Mode This section contains register definitions and opera- tional characteristics of the SPI module. Additional information on SPI operation may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). 8.2.1 OPERATION OF SSP MODULE IN SPI MODE A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3. ...
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... SSPOV SSPEN 85h TRISA — — 94h SSPSTAT SMP CKE Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. 1998 Microchip Technology Inc. PIC16C62B/72A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF — ...
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... PIC16C62B/72A 2 8.3 SSP I C Operation 2 The SSP module mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifica- tions as well as 7-bit and 10-bit addressing ...
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... Note:Shaded cells show the conditions where the user software did not properly clear the overflow condition. 1998 Microchip Technology Inc. PIC16C62B/72A ‘1111 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmit- ter: 1 ...
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... PIC16C62B/72A 8.3.1.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. 2 FIGURE 8- WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 SDA ...
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... SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) 1998 Microchip Technology Inc. PIC16C62B/72A An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse ...
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... PIC16C62B/72A 8.3.2 MASTER OPERATION Master operation is supported in firmware using inter- rupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of ...
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... Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current 1998 Microchip Technology Inc. PIC16C62B/72A Additional information on the A/D module is available in the PICmicro™ (DS33023). The A/D module has three registers. These registers are: • A/D Result Register (ADRES) • ...
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... PIC16C62B/72A FIGURE 9-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 A 000 A 001 A 010 A 011 A 100 A 101 D 11x A = Analog input D = Digital I/O DS35008A-page 50 U-0 R/W-0 R/W-0 R/W-0 — PCFG2 PCFG1 PCFG0 RA1 RA2 ...
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... FIGURE 9-3: A/D BLOCK DIAGRAM A/D Converter V REF (Reference voltage) 1998 Microchip Technology Inc. PIC16C62B/72A 1. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • ...
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... PIC16C62B/72A 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-4. The source impedance (R ) and the internal sampling switch (R S impedance directly affect the time required to charge the capacitor C ...
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... When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. 1998 Microchip Technology Inc. PIC16C62B/72A 9.3 Configuring Analog Port Pins . The The ADCON1 and TRISA registers control the opera- AD tion of the A/D port pins ...
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... PIC16C62B/72A 9.4 A/D Conversions Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. 9.5 Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- grammed as 1011 and that the A/D module is enabled (ADON bit is set) ...
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... SPECIAL FEATURES OF THE CPU The PIC16C62B/72A devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. These are: • OSC Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) ...
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... PIC16C62B/72A 10.2 Oscillator Configurations 10.2.1 OSCILLATOR TYPES The PIC16CXXX can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • ...
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... SS OSC2/CLKOUT Fosc/4 Recommended values Rext 100 k Cext > 20pF 1998 Microchip Technology Inc. PIC16C62B/72A 10.3 Reset The PIC16CXXX differentiates between various kinds of reset: • Power-on Reset (POR) • MCLR reset during normal operation • MCLR reset during SLEEP • WDT Reset (during normal operation) • ...
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... PIC16C62B/72A FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset V rise DD detect Power-on Reset V DD Brown-out Reset BODEN OST/PWRT OST 10-bit Ripple counter OSC1 (1) PWRT On-chip 10-bit Ripple counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. ...
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... C in the event of MCLR/V PP down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 1998 Microchip Technology Inc. PIC16C62B/72A 10.5 Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out (parameter #33), on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. ...
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... PIC16C62B/72A 10.8 Time-out Sequence On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example mode with the PWRT disabled, there will be no time-out at all ...
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... See Table 10-5 for reset value for specific condition any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. 1998 Microchip Technology Inc. PIC16C62B/72A Power-on Reset, MCLR Resets Brown-out Reset WDT Reset ...
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... PIC16C62B/72A FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... FIGURE 10-10: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1998 Microchip Technology Inc. PIC16C62B/72A ) PWRT T OST Preliminary DS35008A-page 63 ...
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... PIC16C62B/72A 10.10 Interrupts The PIC16C62B/72A devices have sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON< ...
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... SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 1998 Microchip Technology Inc. PIC16C62B/72A 10.11 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt, i.e., W register and STATUS bit INTF register ...
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... PIC16C62B/72A 10.12 Watchdog Timer (WDT) The Watchdog Timer free running on-chip RC oscillator which does not require any external compo- nents. This RC oscillator is separate from the RC oscil- lator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction ...
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... SSP transmit or receive in slave mode (SPI/I 6. USART (synchronous slave mode). 1998 Microchip Technology Inc. PIC16C62B/72A Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
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... PIC16C62B/72A FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = SLEEP fetched Instruction SLEEP Inst( executed Note 1: XT oscillator mode assumed 1024T (drawing not to scale) This delay will not be there for RC osc mode ...
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... Thus, for an oscillator frequency of 4 MHz, the normal instruction 1998 Microchip Technology Inc. PIC16C62B/72A execution time conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time ...
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... PIC16C62B/72A TABLE 11-2 PIC16CXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Both systems will operate across the entire operating speed reange of the PICmicro MCU. 1998 Microchip Technology Inc. PIC16C62B/72A 12.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers ...
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... PIC16C62B/72A provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry- level system development. 12.7 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM simple board which demonstrates the capabilities of several of Microchip’ ...
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... Microchip Technology Inc. PIC16C62B/72A 12.13 MPLAB-C17 Compiler The MPLAB-C17 Code Development System is a complete ANSI ‘C’ compiler and integrated develop- ment environment for Microchip’ ...
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... PIC16C62B/72A TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP Products Emulator Tools DS35008A-page 74 Software Programmers Boards Demo 1998 Microchip Technology Inc. ...
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... DD > pin, inducing currents greater than 80 mA, may cause latch-up. PP should be used when applying a “low” level to the MCLR PIC16C62B-20 PIC16LC62B-04 PIC16C72A-20 PIC16LC72A-04 : 4. 2. 2.7 mA typ 3.8 mA max 1.5 A typ max Freq: 4 MHz max. ...
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... PIC16C62B/72A 13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param Sym Characteristic No. D001 V Supply Voltage DD D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to VDD DD D004A* ensure internal ...
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... This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to this trip point. 1998 Microchip Technology Inc. PIC16C62B/72A Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C -40˚C Min Typ† ...
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... PIC16C62B/72A 13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP modes) ...
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... The leakage current on the MCLR/V levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1998 Microchip Technology Inc. PIC16C62B/72A Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C T -40˚ ...
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... PIC16C62B/72A 13.4 AC (Timing) Characteristics 13.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: ...
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... Standard Operating Conditions (unless otherwise stated) Operating temperature AC CHARACTERISTICS Operating voltage V LC parts operate for commercial/industrial temp’s only. FIGURE 13-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 V Pin 1998 Microchip Technology Inc. PIC16C62B/72A 0˚C T +70˚C A -40˚C T +85˚C A -40˚C T +125˚ ...
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... PIC16C62B/72A 13.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 13-2: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 13-2 EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. 1A Fosc External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note Instruction Cycle Time (Note 1) ...
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... Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note1: Measurements are taken in RC Mode where CLKOUT output 1998 Microchip Technology Inc. PIC16C62B/72A ...
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... PIC16C62B/72A FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins Note: Refer to Figure 13-1 for load conditions. FIGURE 13-5: BROWN-OUT RESET TIMING V DD TABLE 13-4 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, ...
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... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1998 Microchip Technology Inc. PIC16C62B/72A Min Typ† ...
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... PIC16C62B/72A FIGURE 13-7: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) CCP1 (Compare or PWM Mode) Note: Refer to Figure 13-1 for load conditions. TABLE 13-6 CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym Characteristic No. 50* TccL CCP1 input low No Prescaler time With Prescaler 51* TccH CCP1 input high No Prescaler time With Prescaler 52* ...
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... Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. PIC16C62B/72A BIT6 - - - - - -1 ...
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... PIC16C62B/72A FIGURE 13-9: EXAMPLE SPI MASTER MODE TIMING (CKE = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Refer to Figure 13-1 for load conditions. TABLE 13-8 EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. Symbol Characteristic No. 71 TscH SCK input high time ...
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... Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. PIC16C62B/72A MSb ...
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... PIC16C62B/72A FIGURE 13-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Refer to Figure 13-1 for load conditions. TABLE 13-10 EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. Symbol Characteristic No. 70 TssL2scH SCK or SCK input ...
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... SU STO Setup time STOP condition HD STO Hold time * These parameters are characterized but not tested. 1998 Microchip Technology Inc. PIC16C62B/72A Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...
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... PIC16C62B/72A 2 FIGURE 13-13 BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 13-1 for load conditions. 2 TABLE 13- BUS DATA REQUIREMENTS Parameter Sym Characteristic No. 100* T Clock high time HIGH 101* T Clock low time LOW 102* T SDA and SCL rise ...
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... The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes. 1998 Microchip Technology Inc. PIC16C62B/72A Min Typ† Max — — ...
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... PIC16C62B/72A FIGURE 13-14: A/D CONVERSION TIMING BSF ADCON0, GO 134 (T /2) OSC Q4 132 A/D CLK 7 A/D DATA ADRES ADIF GO SAMPLE Note1: If the A/D clock source is selected as RC, a time of T allows the SLEEP instruction to be executed. TABLE 13-14 A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. Standard 130 T A/D clock period AD Extended (LC) ...
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... Graphs and Tables not available at this time. Data is not available at this time but you may reference the PIC16C72 Series Data Sheet (DS39016) DC and AC char- acteristic section which contains data similar to what is expected. 1998 Microchip Technology Inc. PIC16C62B/72A is standard deviation, over the whole temperature range. Preliminary DD ...
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... PIC16C62B/72A NOTES: DS35008A-page 96 Preliminary 1998 Microchip Technology Inc. ...
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... For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1998 Microchip Technology Inc. PIC16C62B/72A Example PIC16C72A-04/SP 9817HAT Example Example PIC16C62B-20/SO 9810/SAA Example PIC16C62B 20I/SS025 9817SBP Preliminary PIC16C72A/JW 9817CAT DS35008A-page 97 ...
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... PIC16C62B/72A 15.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane ...
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... Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length * Controlling Parameter. 1998 Microchip Technology Inc. PIC16C62B/72A INCHES* MIN NOM MAX 0.300 ...
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... PIC16C62B/72A 15.4 K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Units Dimension Limits Pitch p Number of Pins n Overall Pack. Height A Shoulder Height A1 Standoff A2 ‡ Molded Package Length D ‡ Molded Package Width E Outside Dimension E1 Chamfer Distance X Shoulder Radius R1 Gull Wing Radius ...
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... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1998 Microchip Technology Inc. PIC16C62B/72A ...
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... PIC16C62B/72A NOTES: DS35008A-page 102 Preliminary 1998 Microchip Technology Inc. ...
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... Can only transmit one word in SPI mode of enhanced SSP. CCP module CCP does not reset TMR1 when in special event trigger mode. Timer1 module Writing to TMR1L register can cause over- flow in TMR1H register. 1998 Microchip Technology Inc. PIC16C62B/72A PIC16C62A/72 2.5V - 5.5V SSP (4 mode SPI) N/A N/A N/A Preliminary PIC16C62B/72A DS35008A-page 103 ...
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... PIC16C62B/72A APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register fi ...
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... GO/DONE Bit ....................................................... 49, 51 ADCON1 Register .................................................. 10, 49, 50 PCFG2:PCFG0 Bits ................................................... 50 ADRES Register ...................................................... 9, 49, 51 Analog Port Pins. See A/D Analog-to-Digital Converter. See A/D Architecture PIC16C62B/PIC16C72A Block Diagram ...................... 5 Assembler MPASM Assembler .................................................... 73 B Banking, Data Memory .................................................. 8, 11 BOR. See Brown-out Reset Brown-out Reset (BOR) ............................. 55, 57, 59, 60, 61 BOR Enable (BODEN Bit) .......................................... 55 BOR Status (BOR Bit) ...
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... PICSTART Plus Entry Level Development System ........ 71 PIE1 Register ............................................................... 10, 14 ADIE Bit ..................................................................... 14 CCP1IE Bit ................................................................ 14 SSPIE Bit ................................................................... 14 TMR1IE Bit ................................................................ 14 TMR2IE Bit ................................................................ 14 Pinout Descriptions PIC16C62B/PIC16C72A .............................................. 6 PIR1 Register ................................................................ 9, 15 ADIF Bit ..................................................................... 15 CCP1IF Bit ................................................................. 15 SSPIF Bit ................................................................... 15 TMR1IF Bit ................................................................ 15 TMR2IF Bit ................................................................ 15 Pointer, FSR ...................................................................... 18 POR. See Power-on Reset PORTA ...
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... CCPR1H:CCPR1L Registers ..................................... 36 Duty Cycle .................................................................. 36 Example Frequencies/Resolutions ............................ 37 Output Diagram .......................................................... 36 Period ......................................................................... 36 Set-Up for PWM Operation ........................................ 37 1998 Microchip Technology Inc. PIC16C62B/72A TMR2 to PR2 Match ............................................ 31, 36 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 14 TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 15 Q Q-Clock .............................................................................. 36 R RAM. See Data Memory Reader Response ...
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... PIC16C62B/72A WCOL Bit ................................................................... 41 SSPSTAT Register ............................................................ 40 BF Bit ......................................................................... 40 CKE Bit ...................................................................... 40 D/A Bit ........................................................................ 40 P bit ...................................................................... 40, 48 R/W Bit ..................................................... 40, 45, 46 Bit ..................................................................... 40, 48 SMP Bit ...................................................................... 40 UA Bit ......................................................................... 40 Stack .................................................................................. 17 STATUS Register ..................................................... 9, 11 Bit ........................................................................... 11 DC Bit ......................................................................... 11 IRP Bit ........................................................................ 11 PD Bit ................................................................... 11, 57 RP1:RP0 Bits ............................................................. 11 TO Bit ................................................................... 11 Bit ............................................................................ 11 Synchronous Serial Port ...
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... Conferences for products, Development Sys- tems, technical information and more • Listing of seminars and events 1998 Microchip Technology Inc. PIC16C62B/72A Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C62B/72A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... Package Pattern a) PIC16C72A - 04/P 301 = Commercial temp., PDIP package, 4 MHz, normal pattern #301. b) PIC16LC62B - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended V (2) ;V range 4. PIC16C62B - 20I/P = Industrial temp., PDIP (2) ;V range 2.5V to 5.5V DD package, 20MHz, normal V (2) ;V range 4.0V to 5.5V DD (2) ;V range 2.5V to 5.5V DD ...
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... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of MicrochipÕs products as critical components in life support systems is not authorized except with express written approval by Microchip ...