KSC-1000 Kodak, KSC-1000 Datasheet - Page 24

• Manufacturer Part Number: KSC-1000
• Description: Timing Generator Full Program-ability Through a Simple 3-wire Serial Interface Allows Maximum Flexibility in Sensor Operation.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
24
General Setup Register
The General Setup Register controls the following parameters:
Pixels Per Line defines the number of pixels in a
horizontal line. Horizontal clocking ends after the
number of clock cycles entered in this field has
occurred.
buffer, and over-clocked pixels. The Horizontal
Pixel Counter starts at count 0 and counts up to
the number entered in this field – 1. At that point
the vertical clocking interval defined by the
current line table starts.
Line Valid Pixel Start defines the pixel on which
the line valid signal is asserted.
Quadrature Start defines where the LINE_VALID
signal is asserted relative to the PIXCLK signal.
Refer to the Line Valid Quadrature Start
Descriptor Table below for a description of the
functionality of these bits. Line Valid Pixel End
defines the pixel on which the line valid signal is
de-asserted. If Line Valid Pixel Start and Line
Valid Pixel End are programmed to the same
value, the LINE_VALID output will not be
asserted.
CLPDM1_Pix_Start,
PBLK_Pix_Start entries define the pixel on which
these
CLPOB1_Pix_End,
CLPDM1_Pix_End,
PBLK_Pix_End entries define the pixel on which
these signals are de-asserted.
which the signals are enabled are defined in the
frame table. The polarity of the signals is defined
in the Signal Polarity Register, except for PBLK.
PBLK polarity is defined in the frame table. If the
Start and End entries are the same value, the
signals will not be asserted. Note that there are
only a single CLOPB and CLPDM output pins.
The purpose of having CLPOB1, CLOPB2,
CLPDM1, and CLPDM2 register settings is to
permit 2 unique pulse width signals to be used at
different points in the image capture sequence.
K S C - 1 0 0 0 R e v 1 . 0
The
CLPOB1_Pix_Start,
Horizontal Line Length
Line sync start and stop pixel locations
AFE clamping signal start and stop pixel locations
AFE blanking signal start and stop pixel locations
Pixel rate clock signal enables
Pixel rate clock signal drive levels
DLL frequency range select
w w w . k o d a k . c o m / g o / i m a g e r s
signals
This count includes all dark, active,
CLPDM2_Pix_Start,
are
CLPDM2_Pix_End
CLPOB2_Pix_Start,
CLPOB2_Pix_End,
asserted.
The lines on
Line Valid
5 8 5 - 7 2 2 - 4 3 8 5
The
and
and
For example, CLPDM and CLPOB could be
asserted for the entire line during the readout of
dark lines and during the dark pixels of active
image readout lines. If the PBLK signal is used, it
is asserted at its programmed location on the end
of a line, remains asserted during the entire
vertical clocking interval, and is de-asserted at
the programmed location on the new line.
Therefore, the minimum PBLK pulse width is the
vertical clocking interval period + 1 pixel.
There are enable bits for the following signals:
RG, H1_1, H2_1, HLG_1, SHP_1, SHD_1,
ADCLK,
HLG_2, SHP_2, and SHD_2.
signals drives the outputs to the state defined in
the signal polarity register. Setting these signals
allows them to toggle as defined in the frame
tables.
within
PIXCLK_Enable bit functions as a global enable
bit. Setting PIXCLK Enable bit low drives the
PIXCLK output low, while setting the bit high
allows the PIXCLK signal to toggle. The purpose
of the rest of the enable bits is to disable those
signals that are not needed for any given
application.
The High Speed Clock Drive Select bit sets the
output current drive capability of the following
outputs: RG, H1_1, H2_1, HLG_1, SHP_1,
SHD_1, ADCLK, DATACLK, PIXCLK, H1_2,
H2_2, HLG_2, SHP_2, and SHD_2. The 12mA
setting allows for power savings and slower rise
and fall times for those applications that run at
slower clock frequencies.
The DLL Frequency Select bits are used to select
the appropriate DLL.
frequency ranges is described in the register field
below.
E m a i l : i m a g e r s @ k o d a k . c o m
the
The PIXCLK signal is not controlled
DATACLK,
frame
PIXCLK,
table,
The definition of the
therefore
Clearing these
H1_2,
H2_2,
the