74ALVC162827TX Fairchild Semiconductor, 74ALVC162827TX Datasheet

74ALVC162827TX

Manufacturer Part Number

74ALVC162827TX

Description

IC BUFF DVR 20BIT LOW V 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC162827TX.pdf (6 pages)

Specifications of 74ALVC162827TX

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC162827T

74ALVC162827

Low Voltage 20-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

and 26 Series Resistors in the Outputs

General Description

The ALVC162827 contains twenty non-inverting buffers

with 3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is byte controlled. Each byte has NOR

output enables for maximum control flexibility.

The 74ALVC162827 is designed for low voltage (1.65V to

3.6V) V

ALVC162827 is also designed with 26

outputs.

The 74ALVC162827 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O capability up to 3.6V. The

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

resistors in the

DS500698

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

Pin Names

1.65V to 3.6V V

3.6V tolerant inputs and outputs

26 series resistors in outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

–I

–O

3.9 ns max for 3.0V to 3.6V V

4.6 ns max for 2.3V to 2.7V V

8.2 ns max for 1.65V to 1.95V V

Human body model

Machine model

Package Description

Output Enable Input (Active LOW)

Inputs

Outputs

supply operation

200V

2000V

through a pull-up resistor; the minimum

November 2001

Revised November 2001

Description

www.fairchildsemi.com

Related parts for 74ALVC162827TX

74ALVC162827TX Summary of contents

Page 1

... MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation Features 1.65V to 3.6V V supply operation CC 3.6V tolerant inputs and outputs ...

Page 2

Connection Diagram www.fairchildsemi.com Truth Tables Inputs – Inputs – ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PL 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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