PIC16C76-10/JW Microchip Technology, PIC16C76-10/JW Datasheet
PIC16C76-10/JW
Related parts for PIC16C76-10/JW
PIC16C76-10/JW Summary of contents
Page 1
... CMOS Microcontrollers with A/D Converter Devices included in this data sheet: • PIC16C72 • PIC16C74A • PIC16C73 • PIC16C76 • PIC16C73A • PIC16C77 • PIC16C74 PIC16C7X Microcontroller Core Features: • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • ...
Page 2
... OSC1/CLKIN 9 20 OSC2/CLKOUT 10 19 RC0/T1OSO/T1CKI 11 18 RC1/T1OSI/CCP2 12 17 RC2/CCP1 13 16 RC3/SCK/SCL 14 15 PIC16C73 PIC16C73A PIC16C76 DS30390E-page 2 RB7 MCLR/V RB6 RA0/AN0 RB5 RA1/AN1 RB4 RA2/AN2 RB3 RA3/AN3/V REF RB2 RA4/T0CKI RB1 RA5/SS/AN4 RB0/INT V V OSC1/CLKIN DD V OSC2/CLKOUT SS RC7 ...
Page 3
... RB0/INT PLCC RA4/T0CKI 7 RA5/SS/AN4 8 RE0/RD/AN5 9 RE1/WR/AN6 10 PIC16C74 RE2/CS/AN7 PIC16C74A OSC1/CLKIN 14 PIC16C77 OSC2/CLKOUT 15 RC0/T1OSO/T1CKI 1997 Microchip Technology Inc RC0/T1OSO/T1CKI 3 31 OSC2/CLKOUT 4 30 OSC1/CLKIN PIC16C74 RE2/CS/AN7 DD ...
Page 4
... Special Features of the CPU ..................................................................................................................................................... 129 15.0 Instruction Set Summary............................................................................................................................................................ 147 16.0 Development Support ................................................................................................................................................................ 163 17.0 Electrical Characteristics for PIC16C72 ..................................................................................................................................... 167 18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183 19.0 Electrical Characteristics for PIC16C73A/74A ........................................................................................................................... 201 20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219 21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241 22.0 Packaging Information ............................................................................................................................................................... 251 Appendix A: ................................................................................................................................................................................... 263 Appendix B: Compatibility ...
Page 5
... The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each device has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Cap- ture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be confi ...
Page 6
... SPI/I C SPI/I C — — 2.5-6.0 3.0-5.5 Yes Yes Yes Yes 28-pin SDIP, 28-pin SDIP, SOIC, SSOP SOIC, SSOP PIC16C76 PIC16C77 368 368 TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 SPI/I C, USART SPI/I C, USART — Yes 5 8 ...
Page 7
... EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before produc- tion shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP Microchip offers a unique programming service where a few user-defi ...
Page 8
... PIC16C7X NOTES: DS30390E-page 8 1997 Microchip Technology Inc. ...
Page 9
... PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 The PIC16CXX can directly or indirectly address its register files or data memory. All special function regis- ters, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (sym- ...
Page 10
... MUX Power-up Timer Oscillator ALU Power-on 8 Reset Watchdog W reg Timer Brown-out Reset Timer2 CCP1 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/SS/AN4 PORTB RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 1997 Microchip Technology Inc. ...
Page 11
... FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC16C73 192 x 8 PIC16C73A 192 x 8 PIC16C76 368 EPROM Program Memory Program 14 Bus Instruction reg 8 Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 CCP1 CCP2 Note 1: Higher order bits are from the STATUS register ...
Page 12
... Timer2 A/D Synchronous USART Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/SS/AN4 PORTB RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD7/PSP7:RD0/PSP0 PORTE RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 1997 Microchip Technology Inc. ...
Page 13
... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1997 Microchip Technology Inc. I/O/P Buffer ...
Page 14
... RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input 2 C modes. 1997 Microchip Technology Inc. ...
Page 15
... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1997 Microchip Technology Inc. I/O/P Buffer ...
Page 16
... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. — These pins are not internally connected. These pins should be left unconnected. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input 2 C modes mode). 1997 Microchip Technology Inc. ...
Page 17
... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 1997 Microchip Technology Inc. 3.2 Instruction Flow/Pipelining An “ ...
Page 18
... PIC16C7X NOTES: DS30390E-page 18 1997 Microchip Technology Inc. ...
Page 19
... PIC16C73A 0000h-0FFFh PIC16C74 0000h-0FFFh PIC16C74A 0000h-0FFFh PIC16C76 0000h-1FFFh PIC16C77 0000h-1FFFh For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h ...
Page 20
... PIC16C7X FIGURE 4-3: PIC16C76/77 PROGRAM MEMORY MAP AND STACK PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-Chip Page 0 On-Chip Page 1 On-Chip Page 2 Page 3 On-Chip DS30390E-page 20 4.2 Data Memory Organization Applicable Devices 72 73 73A 74 74A 76 77 The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers ...
Page 21
... ADCON0 ADCON1 20h General General Purpose Purpose Register Register 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 1997 Microchip Technology Inc. FIGURE 4-5: File File Address Address 00h (1) 80h 01h 81h 02h 82h 03h 83h 04h ...
Page 22
... Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'. Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C76/77. DS30390E-page 22 (*) (*) Indirect addr ...
Page 23
... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. 1997 Microchip Technology Inc. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the “ ...
Page 24
... UA BF --00 0000 --00 0000 — — — — — — — — — — — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
Page 25
... PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 ...
Page 26
... UA BF --00 0000 --00 0000 — — — — — — TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
Page 27
... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. ...
Page 28
... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. ...
Page 29
... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. ...
Page 30
... Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in sub- traction. See the SUBLW and SUBWF instructions for examples. R-1 R/W-x R/W-x R/W bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
Page 31
... Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 ...
Page 32
... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). R/W-0 R/W-0 R/W-0 R/W-x RBIE T0IF INTF RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
Page 33
... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 1997 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 ...
Page 34
... Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. DS30390E-page 34 R/W-0 R/W-0 R/W-0 R/W-0 SSPIE CCP1IE TMR2IE TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
Page 35
... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt ...
Page 36
... GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 36 R/W-0 R/W-0 R/W-0 R/W-0 SSPIF CCP1IF TMR2IF TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
Page 37
... U-0 U-0 U-0 U-0 — — — — bit7 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1997 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — — — CCP2IE bit0 PIC16C7X R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 38
... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. U-0 U-0 U-0 R/W-0 — — — CCP2IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
Page 39
... Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Brown-out Reset is not implemented on the PIC16C73/74. 1997 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred ...
Page 40
... Note: PIC16C7X devices with 4K or less of pro- gram GOTO, CALL PCLATH<4>. The use of PCLATH<4> general purpose read/write bit is not rec- Opcode <10:0> ommended since this may affect upward compatibility with future products. memory ignore paging bit 1997 Microchip Technology Inc. ...
Page 41
... Data Memory 7Fh Bank 0 For register file map detail see Figure 4-4, and Figure 4-5. 1997 Microchip Technology Inc. 4.5 Indirect Addressing, INDF and FSR Registers Applicable Devices 72 73 73A 74 74A 76 77 The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. ...
Page 42
... PIC16C7X NOTES: DS30390E-page 42 1997 Microchip Technology Inc. ...
Page 43
... The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 5-1: INITIALIZING PORTA BCF STATUS, RP0 ; BCF STATUS, RP1 ; PIC16C76/77 only CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 ...
Page 44
... Input/output or slave select input for synchronous serial port or analog input Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 RA2 — — — PCFG2 PCFG1 Value on: Value on all Bit 1 Bit 0 POR, other resets BOR RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
Page 45
... enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). 1997 Microchip Technology Inc. Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin con- fi ...
Page 46
... Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C72/ 73A/74A/76/77 weak P pull-up Data Latch D Q I/O (1) CK pin TRIS Latch D Q TTL CK Input Buffer ST Buffer RD TRIS Latch Port Port EN Q3 and 1997 Microchip Technology Inc. ...
Page 47
... PORTB RB7 RB6 86h, 186h TRISB PORTB Data Direction Register 81h, 181h OPTION RBPU INTEDG Legend unknown unchanged. Shaded cells are not used by PORTB. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RB5 RB4 RB3 RB2 RB1 ...
Page 48
... The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 5-3: INITIALIZING PORTC BCF STATUS, RP0 ; Select Bank 0 BCF STATUS, RP1 ; PIC16C76/77 only CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ...
Page 49
... TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 PIC16C7X Value on: Value on all ...
Page 50
... I/O pin CK Data Latch D Q Schmitt CK Trigger input TRIS Latch buffer RD TRIS and Function Value on: Value on all Bit 0 POR, other resets BOR RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 1997 Microchip Technology Inc. ...
Page 51
... Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output 1997 Microchip Technology Inc. Note Power-on Reset these pins are con- figured as analog inputs. FIGURE 5-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) ...
Page 52
... Device is selected Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 — PORTE Data Direction Bits — — PCFG2 PCFG1 Value on: Value on all Bit 0 POR, other resets BOR RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
Page 53
... Instruction MOVWF PORTB MOVF PORTB,W fetched write to PORTB RB7:RB0 Instruction executed MOVWF PORTB write to PORTB 1997 Microchip Technology Inc. EXAMPLE 5-4: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB<7:4> Inputs ; ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; ; BCF PORTB, 7 ...
Page 54
... DIAGRAM (PARALLEL SLAVE PORT) Data bus PORT CK TTL PORT One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes to V 1997 Microchip Technology Inc. RDx pin RD TTL CS TTL WR TTL and ...
Page 55
... PIR1 PSPIF ADIF RCIF 8Ch PIE1 PSPIE ADIE RCIE 9Fh ADCON1 — — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. 1997 Microchip Technology Inc Bit 4 Bit 3 ...
Page 56
... PIC16C7X NOTES: DS30390E-page 56 1997 Microchip Technology Inc. ...
Page 57
... Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C72, PIC16C73/73A, PIC16C76/77 each have three timer modules. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer overflow). Each of these modules is explained in full detail in the following sections. The timer modules are: • ...
Page 58
... PIC16C7X NOTES: DS30390E-page 58 1997 Microchip Technology Inc. ...
Page 59
... Fetch T0 T0+1 TMR0 Instruction Executed 1997 Microchip Technology Inc. Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The pres- caler assignment is controlled in software by control bit PSA (OPTION< ...
Page 60
... FFh 00h Inst (PC+1) Inst (PC) Dummy cycle PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 PC+6 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 1997 Microchip Technology Inc. ...
Page 61
... Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1997 Microchip Technology Inc. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical ...
Page 62
... Timer0 will clear the prescaler count, but will not change the prescaler assignment SYNC Cycles PSA 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow 1997 Microchip Technology Inc. ...
Page 63
... PEIE 10Bh,18Bh 81h,181h OPTION RBPU INTEDG 85h TRISA — — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 1997 Microchip Technology Inc. BSF STATUS, RP0 ;Bank 1 MOVLW b'xx0x0xxx' ;Select clock source and prescale value of MOVWF OPTION_REG ...
Page 64
... PIC16C7X NOTES: DS30390E-page 64 1997 Microchip Technology Inc. ...
Page 65
... OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1997 Microchip Technology Inc. In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal “reset input”. This reset can be generated by either of the two CCP modules (Section 10 ...
Page 66
... Refer to the appropriate electrical specifica- tions, parameters 40, 42, 45, 46, and 47. 0 TMR1L 1 TMR1ON T1SYNC on/off (3) 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized clock input Synchronize det 2 SLEEP input 1997 Microchip Technology Inc. ...
Page 67
... Reading the 16-bit value requires some care. Example 8 example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped. 1997 Microchip Technology Inc. PIC16C7X EXAMPLE 8-1: READING A 16-BIT FREE- RUNNING TIMER ; All interrupts are disabled ...
Page 68
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Value on: Value on Bit 1 Bit 0 POR, all other BOR resets 0000 000x 0000 000u INTF RBIF 0000 0000 0000 0000 TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1997 Microchip Technology Inc. ...
Page 69
... TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 9-2 shows the Timer2 control register. 1997 Microchip Technology Inc. 9.1 Timer2 Prescaler and Postscaler Applicable Devices 72 73 73A 74 74A 76 77 The prescaler and postscaler counters are cleared when any of the following occurs: • ...
Page 70
... Value at POR reset Value on: Value on Bit 1 Bit 0 POR, all other BOR resets 0000 000x 0000 000u INTF RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 1997 Microchip Technology Inc. ...
Page 71
... The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None 1997 Microchip Technology Inc. PIC16C7X CCP1 module: Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. ...
Page 72
... CCP1IF following any such change in operating mode Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Capture Enable TMR1H TMR1L CCP1CON<3:0> 1997 Microchip Technology Inc. ...
Page 73
... RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select 1997 Microchip Technology Inc. 10.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level ...
Page 74
... Maximum PWM resolution (bits) for a given PWM frequency: Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared. • OSC (TMR2 prescale value) Tosc • (TMR2 prescale value OSC log F PWM = bits log(2) 1997 Microchip Technology Inc. ...
Page 75
... Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. 1997 Microchip Technology Inc. In order to achieve higher resolution, the PWM fre- quency must be decreased ...
Page 76
... TMR2IE TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1997 Microchip Technology Inc. ...
Page 77
... C mode works the same in all PIC16C7X devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C76/77 and the other PIC16C7X devices. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C76/77 and the other PIC16C7X devices ...
Page 78
... C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30390E-page 78 Applicable Devices 72 73 73A 74 74A 76 77 PIC16C74, R-0 R-0 R-0 R mode only mode only Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 79
... C firmware controlled Master Mode (slave idle) 2 1110 = I C slave mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C slave mode, 10-bit address with start and stop bit interrupts enabled 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 R/W-0 R/W-0 R/W-0 R/W-0 ...
Page 80
... Bank 0 ;W reg = contents ;of SSPBUF ;Save in user RAM ;W reg = contents ; of TXDATA ;New data to xmit Internal data bus Write SSPBUF reg SSPSR reg shift bit0 clock Enable Edge 2 Clock Select SSPM3:SSPM0 TMR2 output 4 2 Edge Select T Prescaler CY 4, 16, 64 1997 Microchip Technology Inc. ...
Page 81
... Serial Input Buffer (SSPBUF register) Shift Register (SSPSR) MSb PROCESSOR 1 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor broadcast data by the software protocol ...
Page 82
... Value on: Value on Bit 0 POR, all other BOR resets RBIF 0000 000x 0000 000u 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 BF --00 0000 --00 0000 1997 Microchip Technology Inc. ...
Page 83
... SPI Mode for PIC16C76/77 This section contains register definitions and opera- tional characteristics of the SPI module on the PIC16C76 and PIC16C77 only. FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77) R/W-0 R/W-0 R-0 R-0 SMP CKE D/A P bit7 bit 7: SMP: SPI data input sample phase ...
Page 84
... PIC16C7X FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77) R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP bit7 bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode new byte is received while the SSPBUF register is still holding the previous data. In case of overfl ...
Page 85
... SPI MODE FOR PIC16C76/77 The SPI mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) RC5/SDO • Serial Data In (SDI) RC4/SDI/SDA • Serial Clock (SCK) RC3/SCK/SCL Additionally a fourth pin may be used when in a slave mode of operation: • ...
Page 86
... Master sends data — Slave sends dummy data • Master sends data — Slave sends data • Master sends dummy data — Slave sends data FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C76/77) SPI Master SSPM3:SSPM0 = 00xxb Serial Input Buffer (SSPBUF) ...
Page 87
... SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO SDI (SMP = 0) bit7 SDI (SMP = 1) bit7 SSPIF FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C76/77) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO SDI (SMP = 0) bit7 SSPIF 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 88
... SSPSTAT SMP CKE Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. DS30390E-page 88 Applicable Devices 72 73 73A 74 74A 76 77 bit2 ...
Page 89
... Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A both cases the master generates the clock signal. ...
Page 90
... R/W ACK Wait Data State ACKNOWLEDGE not acknowledge acknowledge Clock Pulse for Acknowledgment acknowledgment signal from receiver Stop ACK Condition 1997 Microchip Technology Inc. ...
Page 91
... A = not acknowledge (SDA high) From master to slave S = Start Condition From slave to master P = Stop Condition 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 SCL is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). This allows a mas- ter to send “ ...
Page 92
... The first device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-23. FIGURE 11-23: CLOCK SYNCHRONIZATION CLK 1 counter CLK reset 2 SCL start counting wait state HIGH period 1997 Microchip Technology Inc. ...
Page 93
... Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly acces- sible • SSP Address Register (SSPADD) 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow ...
Page 94
... Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK SSPBUF Pulse Yes Yes Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 1997 Microchip Technology Inc. ...
Page 95
... SCL S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the byte. ...
Page 96
... SSPIF cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Transmitting Data ACK From SSP interrupt service routine 1997 Microchip Technology Inc. ...
Page 97
... Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unim- plemented, read as '0'. ...
Page 98
... C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear Set RCV_MODE; } 1997 Microchip Technology Inc. ...
Page 99
... For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may expe- rience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77 Low speed Synchronous mode ...
Page 100
... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30390E-page 100 U-0 R-0 R-0 R-x — FERR OERR RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 101
... If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. Writing a new value to the SPBRG register, causes the BRG timer to be reset (or cleared), this ensures the BRG does not wait for a timer overflow before output- ting the new baud rate ...
Page 102
... ERROR (decimal 1.203 +0.23 92 2.380 -0.83 46 9.322 -2.90 11 18.64 -2. 111 0.437 - 255 32.768 kHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 51 0.256 -14.67 +0. -6. 0.512 - - 255 0.0020 - 255 1997 Microchip Technology Inc 255 ...
Page 103
... For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. 1997 Microchip Technology Inc. ...
Page 104
... First falling edge after RX pin goes low Second rising edge Samples Samples Start Bit Baud clk for all but start bit Second rising edge 1 2 Samples Bit0 bit1 Samples bit0 3 4 1997 Microchip Technology Inc. ...
Page 105
... FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77) RX (RC7/RX/DT pin) baud CLK x16 CLK 1997 Microchip Technology Inc. Start bit Baud CLK for all but start bit Samples PIC16C7X Bit0 DS30390E-page 105 ...
Page 106
... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR regis- ter. Data Bus TXREG register 8 MSb LSb (8) 0 TSR register TRMT TX9 TX9D Pin Buffer and Control RC6/TX/CK pin SPEN 1997 Microchip Technology Inc. ...
Page 107
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc 9-bit transmission is desired, then set transmit bit TX9 ...
Page 108
... MSb Stop (8) Data RX9 Recovery RX9D RCREG register RCIF Interrupt RCIE Start Stop bit7/8 Stop bit bit0 bit7/8 bit bit WORD 2 WORD 1 RCREG RCREG FERR LSb 0 1 Start FIFO 8 Data Bus Start bit Stop bit7/8 bit 1997 Microchip Technology Inc. ...
Page 109
... Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE was set ...
Page 110
... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 1997 Microchip Technology Inc. ...
Page 111
... Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF SSPIF CCP1IF ...
Page 112
... TRMT Value on: Value on all Bit 0 POR, other Resets BOR 0000 0000 0000 0000 TMR1IF 0000 -00x 0000 -00x RX9D 0000 0000 0000 0000 0000 0000 0000 0000 TMR1IE 0000 -010 0000 -010 TX9D 0000 0000 0000 0000 1997 Microchip Technology Inc. ...
Page 113
... CREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1997 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 bit4 ...
Page 114
... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. 1997 Microchip Technology Inc. ...
Page 115
... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 116
... PIC16C7X NOTES: DS30390E-page 116 1997 Microchip Technology Inc. ...
Page 117
... A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6, and 7 are implemented on the PIC16C74/74A/77 only. 1997 Microchip Technology Inc. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’ ...
Page 118
... V D REF R/W Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset (1) (1) (1) V RE1 RE2 REF RA3 RA3 RA3 D D — 1997 Microchip Technology Inc. ...
Page 119
... FIGURE 13-3: A/D BLOCK DIAGRAM A/D Converter V REF (Reference voltage) Note 1: Not available on PIC16C72/73/73A/76. 1997 Microchip Technology Inc. 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • ...
Page 120
... IC I leakage V = 0.6V T 500 has no REF ) is HOLD delay must complete before acqui- AD MINIMUM REQUIRED ACQUISITION TIME + [(Temp - 25 C)(0.05 s/ C)] CAP ( ln(1/511 HOLD = DAC capacitance = 51 Sampling Switch ( k ) 1997 Microchip Technology Inc. ...
Page 121
... For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. 1997 Microchip Technology Inc. 13.3 Configuring Analog Port Pins Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 122
... After the A/D conversion is aborted required before the next acquisition is started. After this 2T wait, an acquisition is automatically started on AD the selected channel. ; Select Bank 1 ; PIC16C76/77 only ; Configure A/D inputs ; Enable A/D interrupts ; Select Bank Clock, A/D is on, Channel 0 is selected ; ; Clear A/D interrupt flag bit ...
Page 123
... N)( OSC Note 1: PIC16C7X devices have a minimum T 1997 Microchip Technology Inc. Since the T AD user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 13-3 shows a comparison of time required for a conversion with 4-bits of resolution, ver- sus the 8-bit resolution conversion ...
Page 124
... REF The value that is in the ADRES register is not modified DD for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset should be derived from the device oscil kept away from on-chip OSC 1997 Microchip Technology Inc. , ...
Page 125
... The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage ( Analog V /256 (Figure 13-5). AIN REF 1997 Microchip Technology Inc. FIGURE 13-5: A/D TRANSFER FUNCTION FFh FEh 04h 03h 02h 01h 00h 13 ...
Page 126
... PORTA Data Direction Register Yes Wait Value on: Value on all Bit 0 POR, other Resets BOR RBIF 0000 000x 0000 000u -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 --0x 0000 --0u 0000 RA0 --11 1111 --11 1111 1997 Microchip Technology Inc. ...
Page 127
... TRISE IBF OBF Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE ...
Page 128
... PIC16C7X NOTES: DS30390E-page 128 1997 Microchip Technology Inc. ...
Page 129
... RC oscillator oscillator oscillator oscillator 1997 Microchip Technology Inc. the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay (nominal) on power-up only, designed to keep the part in reset while the power sup- ply stabilizes ...
Page 130
... Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30390E-page 130 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 (2) (1) (1) Register: CONFIG Address 2007h bit0 1997 Microchip Technology Inc. ...
Page 131
... Note 1: A series resistor may be required for AT strip cut crystals. FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from ext. system PIC16CXX Open OSC2 1997 Microchip Technology Inc. TABLE 14-1: Ranges Tested: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16.0 MHz These values are for design guidance only ...
Page 132
... OSC2/CLKOUT pin, and can be used for test pur- poses or to synchronize other logic (see Figure 3-4 for waveform). FIGURE 14-7: RC OSCILLATOR MODE V DD Rext Cext PIC16CXX V SS CLKIN Fosc/4 for given Rext/ DD values. DD Internal OSC1 clock PIC16CXX OSC2/CLKOUT 1997 Microchip Technology Inc. ...
Page 133
... Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77. 3: See Table 14-3 and Table 14-4 for time-out situations. 1997 Microchip Technology Inc. A simplified block diagram of the on-chip reset circuit is shown in Figure 14-8. The PIC16C72/73A/74A/76/77 have a MCLR noise fil- ter in the MCLR reset path. The fi ...
Page 134
... Brown-out Reset is enabled. cal brown-out situations < falls below 4.0V (3.8V - 4.2V range) for falls below DD rises above BV . The DD DD drops below DD rises above Figure 14-9 shows typi- BV Max Min Max Min Max Min. DD 1997 Microchip Technology Inc. , ...
Page 135
... Legend unchanged unknown 1997 Microchip Technology Inc. 14.4.6 POWER CONTROL/STATUS REGISTER (PCON) Applicable Devices 72 73 73A 74 74A 76 77 The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is not imple- mented on the PIC16C73 or PIC16C74. ...
Page 136
... PCON Register PIC16C72/73A/74A/76/77 ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu ( (3) (3) uuuq quuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---u uuuu 1997 Microchip Technology Inc. ...
Page 137
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. 1997 Microchip Technology Inc. Power-on Reset, MCLR Resets Brown-out Reset ...
Page 138
... WDT Reset 0000 0000 0000 0000 --00 0000 --00 0000 0000 -010 0000 -010 0000 0000 0000 0000 ---- -000 ---- -000 - = unimplemented bit, read as '0 value depends on condition Wake-up via WDT or Interrupt uuuu uuuu --uu uuuu uuuu -uuu uuuu uuuu ---- -uuu 1997 Microchip Technology Inc. ...
Page 139
... FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc. T PWRT T OST T PWRT T OST ) DD T PWRT T OST PIC16C7X ...
Page 140
... Internal brown-out detection on the PIC16C72/73A/74A/76/77 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. PROTECTION CIRCUIT 10k MCLR 40k PIC16CXX DD PROTECTION CIRCUIT MCLR 40k PIC16CXX is below a certain level 0.7V V • 1997 Microchip Technology Inc. ...
Page 141
... The exact latency depends when the interrupt event occurs (Figure 14- 17). The latency is the same for one or two cycle 1997 Microchip Technology Inc. PIC16C7X instructions. Individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the GIE bit ...
Page 142
... PIC16C72 Yes Yes Yes PIC16C73 Yes Yes Yes PIC16C73A Yes Yes Yes PIC16C74 Yes Yes Yes PIC16C74A Yes Yes Yes PIC16C76 Yes Yes Yes PIC16C77 Yes Yes Yes FIGURE 14-17: INT PIN INTERRUPT TIMING OSC1 CLKOUT 3 4 INT pin 1 INTF flag 5 (INTCON< ...
Page 143
... PCLATH SWAPF STATUS_TEMP,W MOVWF STATUS SWAPF W_TEMP,F SWAPF W_TEMP,W 1997 Microchip Technology Inc. 14.6 Context Saving During Interrupts Applicable Devices 72 73 73A 74 74A 76 77 During an interrupt, only the return PC value is saved flag bit INTF on the stack. Typically, users may wish to save key reg- isters during an interrupt i ...
Page 144
... MUX PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) CP1 CP0 BODEN PWRTE INTEDG T0CS T0SE PSA = Min., Temperature = Max., and DD PS2:PS0 To TMR0 (Figure 7-6) PSA Bit 2 Bit 1 Bit 0 (1) WDTE FOSC1 FOSC0 PS2 PS1 PS0 1997 Microchip Technology Inc. ...
Page 145
... Special event trigger (Timer1 in asynchronous mode using an external clock). 8. USART (synchronous slave mode). 1997 Microchip Technology Inc. Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 146
... FIGURE 14-21: TYPICAL IN-CIRCUIT SERIAL External Connector Signals + CLK Data I 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h (see programming IL IHH PROGRAMMING CONNECTION To Normal Connections PIC16CXX MCLR/V PP RB6 RB7 Normal Connections 1997 Microchip Technology Inc. ...
Page 147
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1997 Microchip Technology Inc. PIC16C7X The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 148
... Z 11 1000 kkkk kkkk 1 11 00xx kkkk kkkk 2 00 0000 0000 1001 2 11 01xx kkkk kkkk 2 00 0000 0000 1000 0000 0110 0011 1 C,DC,Z 11 110x kkkk kkkk 1010 kkkk kkkk 1997 Microchip Technology Inc. Notes 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 ...
Page 149
... Q1 Q2 Decode Read register 'f' Example ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 1997 Microchip Technology Inc. ANDLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Q Cycle Activity Process Write to data W Example ANDWF ...
Page 150
... Process No- register 'f' data Operation (2nd Cycle No- No- No- No- Operation Operation Operation Operation HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> address TRUE if FLAG<1>= address FALSE 1997 Microchip Technology Inc. ...
Page 151
... Operation Example HERE BTFSC FALSE GOTO • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> FLAG<1> 1997 Microchip Technology Inc. CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: instruction. CY Words Cycles: Process No- Q Cycle Activity: ...
Page 152
... Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set Decode No- Process Clear Operation data WDT Counter CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler 1997 Microchip Technology Inc. ...
Page 153
... Q Cycle Activity Decode Read register 'f' Example DECF CNT, 1 Before Instruction CNT = Z = After Instruction CNT = Z = 1997 Microchip Technology Inc. DECFSZ Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description Words: Process Write to data destination Cycles: Q Cycle Activity: 0x13 If Skip: ...
Page 154
... If ' the result is placed in the W register the result is placed back in register 'f Decode Read Process Write to register data destination 'f' INCF CNT, 1 Before Instruction CNT = 0xFF After Instruction CNT = 0x00 1997 Microchip Technology Inc. ...
Page 155
... Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT address CONTINUE if CNT address HERE +1 1997 Microchip Technology Inc. IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: dfff ffff Words: Cycles: Q Cycle Activity: CY Example Q3 Q4 Process Write to data ...
Page 156
... MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register . ' Decode Read Process Write register data register 'f' 'f' MOVWF OPTION_REG Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 1997 Microchip Technology Inc. ...
Page 157
... PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1997 Microchip Technology Inc. RETFIE Syntax: Operands: Operation: Status Affected: 0xx0 0000 Encoding: Description ...
Page 158
... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction Decode No- No- Pop from Operation Operation the Stack No- No- No- No- Operation Operation Operation Operation RETURN After Interrupt PC = TOS 1997 Microchip Technology Inc. ...
Page 159
... Cycles Cycle Activity Decode Read register 'f' Example RLF REG1,0 Before Instruction REG1 C After Instruction REG1 W C 1997 Microchip Technology Inc. RRF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles Cycle Activity: Process Write to data destination ...
Page 160
... SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative 1997 Microchip Technology Inc. ...
Page 161
... After Instruction REG1 = 0xFF result is negative 1997 Microchip Technology Inc. SWAPF Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description: Words: Cycles Cycle Activity: Process Write to data destination Example TRIS Syntax: Operands: Operation: Status Affected: None ...
Page 162
... If ' the result is stored in the W register the result is stored back in register 'f Decode Read Process Write to register data destination 'f' XORWF REG 1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 1997 Microchip Technology Inc. ...
Page 163
... Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user compliant version of PICMASTER is available for European Union (EU) countries. 1997 Microchip Technology Inc. 16.3 ICEPIC: Low-cost PIC16CXXX In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers ...
Page 164
... MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System. 1997 Microchip Technology Inc. ...
Page 165
... TECH-MP, edition for imple- menting more complex systems. Both versions include Microchip’s fuzzy LAB stration board for hands-on experience with fuzzy logic systems implementation. 1997 Microchip Technology Inc. 16.14 MP-DriveWay Generator MP-DriveWay is an easy-to-use Windows-based Appli- cation Code Generator. With MP-DriveWay you can visually confi ...
Page 166
... PIC16C7X TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP Products Emulator DS30390E-page 166 Tools Software Programmers Boards Demo 1997 Microchip Technology Inc. ...
Page 167
... The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 (except V , MCLR, and RA4) ...
Page 168
... A T +85˚C for industrial and A T +70˚C for commercial A Conditions = 4 MHz 5.5V (Note MHz 5. 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled 4.0V, WDT disabled, - +125 and 1997 Microchip Technology Inc. ...
Page 169
... This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C 0˚C Sym Min Typ† ...
Page 170
... PIN DD impedance A Vss V V PIN DD A Vss XT, HS and PIN DD LP osc configuration 8.5 mA 4. 7.0 mA 4.5V - +125 1.6 mA 4. 1.2 mA 4.5V - +125 C 1997 Microchip Technology Inc. ...
Page 171
... The leakage current on the MCLR/V levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 172
... SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin V SS for all pins except OSC2 for OSC2 output 1997 Microchip Technology Inc. ...
Page 173
... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 174
... Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 50 150 ns — — ns — — ns — — — — — — ns — — ns 1997 Microchip Technology Inc. ...
Page 175
... BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A ...
Page 176
... N = prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7Tosc — 1997 Microchip Technology Inc. ...
Page 177
... TccF CCP1 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A ...
Page 178
... Min — — 10 — — — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — — — 1997 Microchip Technology Inc. ...
Page 179
... T : STOP condition SU STO Setup time STOP condition HD STO Hold time 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...
Page 180
... Only relevant for repeated START condition s s After this period the first clock pulse is generated Note Note Time the bus must be free before a new transmission can s start pF 2 C-bus system, but the requirement 1997 Microchip Technology Inc. ...
Page 181
... Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Min Typ† — ...
Page 182
... LSb (i.e., 20 5.12V) from the last sampled voltage (as stated HOLD — If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed 1997 Microchip Technology Inc. ...
Page 183
... The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 (except V , MCLR ...
Page 184
... Rext in kOhm. T +85˚C for industrial and A T +70˚C for commercial A Conditions = 4 MHz 5.5V (Note MHz 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled and 1997 Microchip Technology Inc. ...
Page 185
... DD 5: Timer1 oscillator (when enabled) adds approximately the specification. This value is from charac- terization and is for design guidance only. This is not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 186
... PIN Pin at hi-imped- PIN DD ance V V PIN XT, HS and LP osc PIN DD configuration I = 8.5 mA 4. 1.6 mA 4. -3.0 mA 4. -1.3 mA 4.5V - +85 C RA4 pin 1997 Microchip Technology Inc. ...
Page 187
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 188
... C specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin 1997 Microchip Technology Inc. ...
Page 189
... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 190
... Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 50 150 ns — — ns — — ns — — — — — — ns — — ns 1997 Microchip Technology Inc. ...
Page 191
... Watchdog Timer Reset * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A Min Typ† ...
Page 192
... N = prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7Tosc — 1997 Microchip Technology Inc. ...
Page 193
... TccF CCP1 and CCP2 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A ...
Page 194
... Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 194 65 62 Min Typ† Max Units 20 PIC16C74 20 PIC16LC74 35 — Conditions — — ns — — ns — — ns — — 1997 Microchip Technology Inc. ...
Page 195
... SDO data output valid after SCK TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 75, 76 ...
Page 196
... STOP Condition Conditions Only relevant for repeated START condition After this period the first clock pulse is generated 1997 Microchip Technology Inc. ...
Page 197
... SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I R released. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 100 101 106 ...
Page 198
... PIC16LC73/74 — 125 126 Min Typ† (DT setup time) 15 — (DT hold time) 15 — 122 Typ† Max Units Conditions — — 100 ns — — — — Max Units Conditions — ns — ns 1997 Microchip Technology Inc. ...
Page 199
... Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Min Typ† — ...
Page 200
... LSb (i.e 5.12V) from the last sampled voltage (as stated HOLD — If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed 1997 Microchip Technology Inc. ...