ISL12027 Intersil Corporation, ISL12027 Datasheet - Page 16

• Manufacturer Part Number: ISL12027
• Manufacturer: Intersil Corporation

Power On Reset
Application of power to the ISL12027 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
When V
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
Watchdog Timer Operation
The watchdog timer timeout period is selectable. By writing a
value to WD1 and WD0, the watchdog timer can be set to 3
different time out periods or off. When the Watchdog timer is
set to off, the watchdog circuit is configured for low power
operation. See Table 6.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode. See Figure 3.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V
voltage (V
below V
V
V
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V
DD
RESET
- It prevents the system microprocessor from starting to
- It prevents the processor from operating prior to
- It allows time for an FPGA to download its configuration
- It prevents communication to the EEPROM, greatly
operate with insufficient voltage.
stabilization of the oscillator.
prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
WD1
line rises above V
1
1
0
0
, then the RESET output will remain asserted low.
DD
RESET
RESET
exceeds the device V
. The reset pulse will timeout 250ms after the
), then generates a RESET pulse if it is
WD0
1
0
1
0
RESET
DD
TABLE 6.
DD
= 1.0V.
16
. If the V
line versus a preset threshold
RESET
DD
DURATION
threshold value for
disabled
250ms
750ms
remains below
1.75s
ISL12027
When the LVR signal is active, unless the part has been
switched into the battery mode
progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I
backup and LVR Operation”.
Serial Communication
Interface Conventions
The device supports the I
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 16.
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 17.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 17.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits of
data. Refer to Figure 18.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
2
C Communications During Battery
2
C Protocol.
,
the completion of an in-
April 17, 2006
FN8232.3