ISL22316 Intersil Corporation, ISL22316 Datasheet - Page 10

• Manufacturer Part Number: ISL22316
• Manufacturer: Intersil Corporation

When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 7-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (127
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22316 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a
non-volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
I
Memory Description
The ISL22316 contains one non-volatile 8-bit register, known as
the Initial Value Register (IVR), and two volatile 8-bit registers,
Wiper Register (WR) and Access Control Register (ACR).
Memory map of ISL22316 is on Table 1. The non-volatile
register (IVR) at address 0, contain initial wiper position and
volatile registers (WR) contain current wiper position.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
2
ADDRESS
C serial interface as described in the following sections.
2
1
0
NON-VOLATILE
TABLE 1. MEMORY MAP
IVR
—
10
Reserved
VOLATILE
ACR
WR
ISL22316
The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically OR ‘d with SHDN pin. When this bit is 0,
DCP is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
I
The ISL22316 supports an I
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22316
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 2). On power-up of the ISL22316 the SDA pin is in the
input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22316 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 16). A START condition is ignored during the
power-up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 17).
2
C Serial Interface
VOL
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
TABLE 2. ACCESS CONTROL REGISTER (ACR)
SHDN
WIP
2
2
C bidirectional bus oriented
0
C interface is conducted by
0
0
0
June 23, 2006
FN6186.0
0