ISL3685 Intersil Corporation, ISL3685 Datasheet
ISL3685
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ISL3685 Summary of contents
Page 1
... RF amplifiers can be directly connected to mixers as bandwidth characteristics attenuate image frequencies. The inherent image rejection of both the transmit and receive functions allows this economic advantage. The ISL3685 is housed Lead QFN package well suited for PCMCIA board and MINI PCI applications. Ordering Information TEMP RANGE ...
Page 2
... Synthesizer Clock, DATA is clocked in on the rising edge of the serial clock, MSB first. 18 REF_BY Synthesizer Reference Frequency Input Bypass, internally DC coupled and requires an external bypass to ground when REF_IN is used as a Single Ended input, requires an external AC coupling capacitor when used as a differential input. 2 ISL3685 ISL3685 (QFN) TOP VIEW ...
Page 3
... LNA Collector Output, requires a bypass capacitance which is resonant with the PC board parasitics. A small resistance (20Ω) in series with the main PC board V capacitors. This ensures the image rejection performance of the LNA is maintained. All GND Circuit Ground Pins (Quantity 6 each). Others 3 ISL3685 DESCRIPTION bus is recommended to provide isolation from other V CC bypass CC ...
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... LO Frequency Range LO Input Drive Level Power/Voltage Gain Noise Figure SSB Input IP3 Input P1dB 4 ISL3685 Thermal Information Thermal Resistance (Typical, Note 1) QFN Package Maximum Junction Temperature (Plastic Package .150 Maximum Storage Temperature Range . . . . . . . . . . -65 For Recommended soldering conditions see Tech Brief TB389. ...
Page 5
... LO to Transmit Amp. Output Feedthrough (Cascaded, No Filter) Preamplifier Output 50Ω VSWR LO 50Ω VSWR Differential IF Input Load IF Input Capacitance (Single Ended) IF Input Resistance (Single Ended) 5 ISL3685 Assumes a direct connection between the LNA and Mixer 374MHz 2075MHz at -6dBm 2 Unless Otherwise Specified (Continued) ...
Page 6
... PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers. 6 ISL3685 (See Notes 4 through 12) TEST CONDITIONS ...
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... Phase Lock Loop Power Enable Enable Power Down. Serial port always on. M(2) Prescaler Select 32/33 64/65. M(3) Charge Pump Current Setting M(4) M(5) Charge Pump Sign M(6) M(7) LD Pin Multiplex Operation M(8) M(13) M(14) Charge Pump Operation/Test M(15) 7 ISL3685 M(2) M(3) M(4) M(5) M(6) M(7) M(8) DESCRIPTION DESCRIPTION B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is * DESCRIPTION M( ...
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... > NOTES: π 11. Phase difference detection range: -2 12. The minimum width pump up and pump down current pulses occur at the D FIGURE 2. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 8 ISL3685 BIT 10 BIT FIGURE 1. SERIAL DATA INPUT TIMING < f ...
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... ISL3685 Evaluation Schematic Diagram LNA_OUT R3 100k LNA_IN LNA_HL GP1 R4 R6 100k 100 PE2 GP2 PRE_OUT PE1 GP3 R5 100k NOTES: L23 is 807 mils from edge of SMA pad to center of component pad. C26 is 381 mils from edge of U1 pin 13 to center of pad. R19 is 37 mils from edge of R17 SMA side to center of pad. ...
Page 10
... ISL3685 Evaluation Schematic Diagram L23 RX_MIX_IN 1.2NH C25 220pF R MX OUT IN GND DRIVER VCC 30 LO VCC DRIVER VCC VCC2+ 25 TX_MX_OUT 24 23 TX_MX_VCC2 DATA LE CLK UP2 GND N/C UP1 N/C 10 ISL3685 (Continued) C27 R36 3.3pF ...
Page 11
... V = 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm Marker 1 = 1.7GHz, -46.4dB Marker 3 = 2.45GHz, -44.1dB Marker 5 = 3.0GHz, -35.4dB FIGURE 5. S12 LNA IN HIGH GAIN 11 ISL3685 SCALE 5dB/DIV 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm Marker 1 = 1.7GHz, 7.0dB Marker 3 = 2.45GHz, 15.3dB Marker ...
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... V = 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker 5 = 3.0GHz, -15.7dB FIGURE 9. S12 LOW GAIN LNA 12 ISL3685 (Continued) SCALE 5dB/DIV 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm Marker 1 = 1.7GHz, -12.4dB Marker 3 = 2.45GHz, -18.9dB Marker ...
Page 13
... Pin = -30dBm NO MATCH NETWORK Marker 1 = 1.7GHz, Real = 7.8Ω , Imaginary = -47.0Ω Marker 3 = 2.45GHz, Real = 15.4Ω , Imaginary = 7.53Ω Marker 5 = 3.0GHz, Real = 37.9Ω , Imaginary = -12.5Ω FIGURE 13. S11 TX PREAMP 13 ISL3685 (Continued 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 1 Marker 1 = 1.7GHz, Real = 21.0Ω , Imaginary = -54.8Ω ...
Page 14
... TEMP = 85 C GAIN 1dB/DIV. 2.7V NF 1dB/DIV. 3.3V GAIN AT CURSOR 14.0dB AT 2.7V, 14.3dB AT 3.3V NOISE FIGURE AT CURSOR 3.9dB AT 2.7V, 3.73dB AT 3.3V RF 2.4GHz FIGURE 17. LNA HIGH SETTING, GAIN AND NF 14 ISL3685 (Continued 3.30V 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm NO MATCH NETWORK 5 Marker 1 = 1.7GHz, Real = 7.2Ω , Imaginary = -27.1Ω ...
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... C 2.7V GAIN 1dB/DIV. NF 1dB/DIV. 3.3V GAIN AT CURSOR 7.7dB AT 2.7V, 7.8dB AT 3.3V NOISE FIGURE AT CURSOR 8.9dB AT 2.7V, 9.0dB AT 3.3V RF 0.365GHz IF 2440.000MHz FIGURE 23. TX MIXER GAIN AND NF 15 ISL3685 (Continued) TYPICAL APPLICATION, TEMP = -40 3.3V GAIN 1dB/DIV. NF 1dB/DIV. 2.7V GAIN AT CURSOR -18.6dB AT 2.7V, -18.0dB AT 3.3V NOISE FIGURE AT CURSOR 17.0dB AT 2.7V, 16.3dB AT 3.3V RF 2.5GHz RF 2.4GHz FIGURE 20 ...
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... IN LOW GAIN) 0.2dB/DIV * * -40 -30 -20 - TEMPERATURE DEGREES ( FIGURE 29. POWER/VOLTAGE GAIN HIGH GAIN MODE 16 ISL3685 (Continued) -40 -30 -20 -10 FIGURE 26. RECEIVE TOTAL SUPPLY CURRENT * * -40 -30 -20 - FIGURE 28. TRANSMIT TOTAL SUPPLY CURRENT * * - 0.5mA/DIV ...
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... TEMPERATURE DEGREES ( FIGURE 33. RX OUTPUT IM3 AT -5dBm INPUT TONES * * * -40 -30 -20 - TEMPERATURE ( FIGURE 35. INPUT P1dB LOW GAIN MODE 17 ISL3685 (Continued 2. 3. 100 -40 -30 -20 - FIGURE 32. POWER/VOLTAGE GAIN LOW GAIN MODE * * ...
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... TEMPERATURE DEGREES ( FIGURE 37. POWER CONVERSION GAIN * * -40 -30 -20 - TEMPERATURE DEGREES ( FIGURE 39. OUTPUT P1dB 18 ISL3685 (Continued) 0.2dB/DIV * * -40 -30 -20 - 0.2dB/DIV * * - FIGURE 40 TRANSMIT AMP OUTPUT FEEDTHROUGH 0.2dB/DIV * * ...
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... Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 19 ISL3685 L44.7x7 44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKD-1 ISSUE C) ...