ISL5314 Intersil Corporation, ISL5314 Datasheet
ISL5314
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ISL5314 Summary of contents
Page 1
... TM Data Sheet Direct Digital Synthesizer The 14-bit ISL5314 provides a complete Direct Digital Synthesizer (DDS) system in a single 48-pin LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital to analog converter) are integrated into a stand alone DDS. ...
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... SDATA, SSYNC, SCLK (IN PARALLEL CONTROL MODE, SERIAL CONTROL CAN ALSO BE USED IF DESIRED.) WRITE CLOCK (WR) WRITE ENABLE 4 A3:A0 BUS C7:C0 BUS ENOFR 4 DGND 5 CLK ISL5314 6 DVDD 7 RESET 8 UPDATE 9 COMPOUT 10 REFLO 11 REFIO 0.1µF 0.1µF R SET AV PP 2kΩ ...
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... Functional Description The ISL5314 is an NCO with an integrated 14-bit DAC designed to run in excess of 125MSPS. The NCO is a 16-bit output design, which is rounded to fourteen bits for input to the DAC. The frequency control is the sum of a 48-bit center frequency word, a 48-bit offset frequency word, and a 40-bit serially loaded tuning word ...
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... BPSK or QPSK modulation. These pins can also be used for providing sine/cosine when using two ISL5314s together as quadrature local oscillators. The ENOFR pin enables or zeros the offset frequency word to the phase accumulator and can be used for FSK or MSK modulation ...
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... ISL5314 depends on the way the user programs the device to do FSK, and the form of FSK. For example, simple BFSK is efficiently performed with the ISL5314 by loading the center frequency register with one fre- quency, the offset frequency register with another frequency, and toggling the ENOFR (enable offset frequency register) pin ...
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... CLK. CLK Quadrature Local Oscillators Two ISL5314s can be used as sine/cosine generators for quadrature local oscillator applications important to note that the phase accumulator feedback needs to be zeroed in both devices desired that both DDSs restart with a known phase, which is determined by the use of the phase control pins, PH1 and PH0 ...
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... IOUTFS = 20mA IOUTFS = 2mA AC CHARACTERISTICS Spurious Free Dynamic Range, f CLK SFDR Within a Window (Notes CLK f CLK 7 ISL5314 Thermal Information Thermal Resistance (Typical, Note 1) LQFP Package Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 + 0.3V Maximum Storage Temperature Range . . . . . . . . . . - 0.3V Maximum Lead Temperature (Soldering 10s 300 DD o ...
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... WW Data Setup Time, t Between DATA and WR (Note 3) DS Data Hold Time, t Between DATA and WR (Note 3) DH Address Setup Time, t Between ADDR and WR (Note ISL5314 = DV = +5V (unless otherwise noted for All Typical Values (Continued) A TEST CONDITIONS = 125MSPS 40.4MHz OUT = 125MSPS ...
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... SSYNC Setup Time, t Between SSYNC and SCLK. See Figure 6 Timing Diagrams. SSS (Note 3) SSYNC Hold Time, t Between SSYNC and SCLK. See Figure 6 Timing Diagrams. SSH (Note 3) 9 ISL5314 = DV = +5V (unless otherwise noted for All Typical Values (Continued) A TEST CONDITIONS = Internal 1 ...
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... Definition of Specifications Differential Non-Linearity (DNL) is the measure of the step size output deviation from code to code. Ideally the step size should be one LSB. A DNL specification of one LSB or less guarantees monotonicity. 10 ISL5314 = DV = +5V (unless otherwise noted for All Typical Values (Continued) ...
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... UPDATE ANALOG OUT FIGURE 3. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH) 11 ISL5314 from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25Ω due to the parallel resistance of the 50Ω loading on the output and the oscilloscope’ ...
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... ONE CLK RISING EDGE REQUIRED WHILE RESET LOW CLK (f ) CLK RESET ANALOG OUT CLK (f ) CLK ENOFR ANALOG OUT FIGURE 6. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH) 12 ISL5314 DON’T CARE PREVIOUS FREQ ...
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... CLK DON’T CARE (ASSUMED CONTINUOUSLY RUNNING) ANALOG OUT FIGURE 8. SERIAL PROGRAMMING, SYNC LATE BURST MODE (REPRESENTS MINIMUM SCLKS REQUIRED; SCLK CAN FREE RUN); CONTROL REGISTER 12 IS SET TO 0000 00XX. 13 ISL5314 t SDW t SDH SERIAL DATA (8 BITS SHOWN; MAX IS 40) SCLK EDGES = SERIAL BITS + 3 ...
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... ISL5314 PIN DESCRIPTION 8-bit processor input data bus the MSB. Data is written to the control register selected on A(3:0) on the rising edge of WR when WE is active. Write clock for the processor interface. Parallel data is clocked into the chip on the rising edge of WR ...
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... NCO-to-DAC setup and hold timing control. Write either 11b or 00b to these bits. 15 7:0 Register 15 does not actually exist. Any write to register UPDATE. This function is provided to save one microprocessor control pin from being used for the UPDATE pin, if the user chooses. * b=binary, h=hex 15 ISL5314 DESCRIPTION f CLK /4 output). /4. CLK RESET ...
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... Intersil Corporation 7585 Irvine Center Drive 2401 Palm Bay Rd. Suite 100 Palm Bay, FL 32905 Irvine, CA 92618 TEL: (321) 724-7000 TEL: (949) 341-7000 FAX: (321) 724-7946 FAX: (949) 341-7123 16 ISL5314 Q48.7x7A 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL -B- e SEATING PLANE A NOTES: 0.08 1 ...