PIC16C773 Microchip Technology, PIC16C773 Datasheet - Page 71

• Manufacturer Part Number: PIC16C773
• Description: 28/40-Pin/ 8-Bit CMOS Microcontrollers w/ 12-Bit A/D
• Manufacturer: Microchip Technology

8.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I
bit is set, or the bus is idle with both the S and P bits
clear.
FIGURE 8-17: SSP BLOCK DIAGRAM (I
1999 Microchip Technology Inc.
SDA
SCL
MASTER MODE
2
C bus may be taken when the P
SDA in
Bus Collision
SCL in
Read
Advance Information
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
Clock Arbitration
State counter for
Start bit detect,
2
Stop bit detect
Acknowledge
C MASTER MODE)
Generate
SSPBUF
SSPSR
LSb
Write
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset AKSTAT, PEN (SSPCON2)
PIC16C77X
SSPADD<6:0>
SSPM3:SSPM0,
Baud
rate
generator
DS30275A-page 71