74ABT652CMSAX Fairchild Semiconductor, 74ABT652CMSAX Datasheet - Page 2

• Manufacturer Part Number: 74ABT652CMSAX
• Description: IC TRANSCVR TRI-ST 8BIT 24SSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74ABTr

Specifications of 74ABT652CMSAX

• Logic Type: Transceiver, Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Truth Table
H
L

X
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the ABT652.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW Voltage Level
HIGH Voltage Level
Immaterial
LOW to HIGH Clock Transition
OEAB OEBA
H
H
H
H
X
L
L
L
L
L
L
H
H
H
H
H
H
X
L
L
L
L
CPAB
H or L
H or L
H or L
H or L
 

 
 
X
X
X
Inputs
CPBA
H or L
H or L
H or L
H or L

X
X
X
SAB
X
X
X
X
X
X
X
X
H
H
L
SBA
X
X
X
X
X
X
H
X
X
H
L
Input
Input
Input
Not Specified Input
Output
Output
Input
Output
A
Inputs/Outputs (Note 1)
2
0
thru A
Data on the A or B data bus, or both, can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
7
Output
Input
Not Specified Store A, Hold B
Output
Input
Input
Output
B
0
thru B
7
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Isolation
Store A and B Data
Store A in Both Registers
Hold A, Store B
Store B in Both Registers
Stored B Data to A Bus
Operating Mode