74ALVCH162244T Fairchild Semiconductor, 74ALVCH162244T Datasheet

IC BUFF DVR 16BIT LOW V 48TSSOP

74ALVCH162244T

Manufacturer Part Number
74ALVCH162244T
Description
IC BUFF DVR 16BIT LOW V 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ALVCHr
Datasheet

Specifications of 74ALVCH162244T

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2002 Fairchild Semiconductor Corporation
74ALVCH162244T
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26 Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) V
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with output capability up to 3.6V.
Package
Number
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500632
series
Features
Pin Descriptions
Pin Names
OE
I
O
0
1.65V to 3.6V V
3.6V tolerant control inputs and outputs
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
26 series resistors in outputs
t
Uses patented noise/EMI reduction circuitry
Latch-up conforms to JEDEC JED78
ESD performance:
–I
0
PD
–O
n
15
4.2 ns max for 3.0V to 3.6V V
4.9 ns max for 2.3V to 2.7V V
7.6 ns max for 1.65V to 1.95V V
Human body model
Machine model
15
Package Description
CC
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
supply operation
200V
2000V
September 2001
Revised February 2002
Description
CC
CC
CC
www.fairchildsemi.com

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74ALVCH162244T Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Package Order Number Number 74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Functional Description The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 2) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V 3.3V CC Min Propagation Delay 1.0 PHL PLH Output Enable Time 1.0 PZL PZH Output Disable Time 1.0 PLZ PHZ Capacitance Symbol Parameter C Input ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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