T15M1024A TM tech, T15M1024A Datasheet - Page 7

• Manufacturer Part Number: T15M1024A
• Description: 128K X 8 LOW POWER CMOS STATIC RAM
• Manufacturer: TM tech

TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
READ CYCLE 2
(Chip Enable Controlled)
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition. t
5. Transition is measured 200mV from steady state voltage with load.
6. Device is continuously selected with
TM Technology Inc. reserves the right
to change products or specifications without notice.
V
and from device to device interconnection.
100% tested.
HZ
A d d r e s s
OH
and t
D O U T
or V
OHZ
OL
D
CH
C E 1
C E 2
TE
levels.
OUT
Previous Data Valid
are defined as the time at which the outputs achieve the open circuit condition referenced to
t OH
t AA
CE
t
t
ACE
OLZ
1
=V
IL
.
HZ
t RC
(max.) is less than t
P. 7
Data Valid
This parameter is sampled and not
LZ
(min.) both for a given device
Publication Date: FEB. 2002
t
OHZ
T15M1024A
DON'T CARE
UNDEFINED
Revision:A