IXS839S1T-R Clare, Inc., IXS839S1T-R Datasheet - Page 3

• Manufacturer Part Number: IXS839S1T-R
• Description: Synchronous Buck Mosfet Driver
• Manufacturer: Clare, Inc.

Pin Description and Configurations
SOIC and QFN Top View Pin Configurations
IXS839
N/A
N/A
1
2
3
4
5
6
7
8
PWM
VDD
DLY
BST
IXYS
IXS839A
1
2
4
3
10
3
5
7
8
9
1
2
4
6
IXS839S1
IXS839B
8
6
7
5
10
2
4
5
6
7
8
9
1
3
HGD
SW
PGND
LGD
PGND
Name
PWM
PWM
HGD
HGD
VDD
LGD
BST
DLY
LSD
BST
___
SW
SD
SW
SD
__
1
2
3
4
5
IXS839AQ2
SD
Description
Upper Gate Driver Floating DC Power Terminal for Bootstrap
Capacitor Connection.
TTL-level Input Signal with active pull-down. PWM input to the
Gate Drivers.
Terminal for External Delay Capacitor Connection. Capacitor
to Ground at this pin adds propagation delay from Lower Gate
Driver going Low to the Upper Gate Driver going High.
t
Positive Supply Terminal for Logic and Lower Gate Driver. A
ceramic bypass capacitor of 1uF should be connected from
VDD to PGND.
Lower Gate Driver Output Terminal
Lower Gate Driver DC Power Return Terminal, Logic and
Analog Ground
Upper Gate Driver Floating DC Power Return Terminal
Upper Gate Driver Output Terminal
TTL-level Shut Down Input Signal with active pull-up.
the driver outputs are forced low and I
TTL-level Low Side Shut Down Input Signal with active pull-
up. LSD , when low forces the Lower Gate Driver output low.
When LSD is high, the lower Gate Driver output is enabled.
DLY
3
enables normal operation when high. When
(nS) = C
10
9
8
7
6
DLY
PGND
LGD
VDD
DLY
LSD
(pF) x (0.5nS/pF)
IXS839 / IXS839A / IXS839B
PWM
VDD
LSD
DLY
SD
1
2
3
4
5
IXS839BQ2
DD
is at its minimum.
10
9
8
7
6
SD
HGD
SW
PGND
LGD
BST
is low,