74ABT2541CMTC Fairchild Semiconductor, 74ABT2541CMTC Datasheet

IC BUFF/DVR 8BIT NON-INV 20TSSOP

74ABT2541CMTC

Manufacturer Part Number
74ABT2541CMTC
Description
IC BUFF/DVR 8BIT NON-INV 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet

Specifications of 74ABT2541CMTC

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 15mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74ABT2541CSC
74ABT2541CSJ
74ABT2541CMSA
74ABT2541CMTC
74ABT2541
Octal Buffer/Line Driver with
25: Series Resistors in the Outputs
General Description
The ABT2541 is an octal buffer and line driver designed to
drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented transmit-
ters/receivers. Functionally identical to the ABT541.
The 25
eliminate the need for external resistors.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Schematic of Each Output
Order Number
:
series resistors in the outputs reduce ringing and
Package Number
MSA20
MTC20
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011502
Features
Pin Descriptions
Truth Table
H
L
X
Z
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and
250 pF loads
Guaranteed simultaneously switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus
contention
LOW Voltage Level
Immaterial
High Impedance
HIGH Voltage Level
OE
I
O
0
–I
0
Pin Names
–O
Package Description
OE
1
7
, OE
L
H
X
L
7
1
2
Inputs
OE
Output Enable Input (Active LOW)
Inputs
Outputs
H
L
X
L
2
September 1992
Revised March 2005
H
X
X
Description
L
I
www.fairchildsemi.com
Outputs
H
Z
Z
L

Related parts for 74ABT2541CMTC

74ABT2541CMTC Summary of contents

Page 1

... Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT2541CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT2541CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending “X” to the ordering code. ...

Page 2

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2)  Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State ...

Page 3

DC Electrical Characteristics (SOIC Package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 4

Skew (SOIC Package) Symbol Parameter t Pin to Pin Skew OSHL (Note 14) HL Transitions t Pin to Pin Skew OSLH (Note 14) LH Transitions t Duty Cycle PS (Note 15) LH–HL Skew t Pin to Pin Skew OST (Note ...

Page 5

AC Loading *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide www.fairchildsemi.com Package Number M20B 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide www.fairchildsemi.com Package Number MSA20 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

Related keywords