FMS6416LBF FIDELIX, FMS6416LBF Datasheet

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Low Power SDRAM Rev. 0.4, Aug. ‘07 Revision 0.4 Aug. 2007 C(F)MS6416LBx–75Ex ...

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Document Title 64M(4Mx16) Low Power SDRAM Revision History Revision No. 0.0 Initial Draft 0.1 Revised P/N according to the new P/N system 0.2 Changed min vcc to 1.70V 0.3 Changed tRRD to 15ns 0.4 Add KGD description, minor change Rev. ...

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... DD C(F)MS6416LBx-75Ex 1.70-1.95V Rev. 0.4, Aug. ‘07 - LVCMOS Compatible IO Interface - 54 ball FBGA with 0.8 mm ball pitch - FMS6416LBF : Normal - FMS6416LBG : Pb-Free - FMS6416LBH : Pb-Free & Halogen Free - CMS6416LBW : KGD (Wafer) Functional Description The C(F)MS6416LB Family is high-performance CMOS Dynamic RAMs (DRAM) organized 16. These devices feature advanced circuit design to provide low active current and extremely low standby current ...

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Pin Configuration Rev. 0.4, Aug. ‘07 54 ball 0.8mm pitch FBGA (8mm x 8mm) Top View DQ15 V SS SSQ DQ14 DQ13 V DDQ ...

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Pin Description Symbol Type CLK Input CKE Input /CS Input /CAS, /RAS, /WE Input LDQM, UDQM Input BA0, BA1 Input A0-A11 Input DQ I Supply DDQ V Supply SSQ V Supply DD V Supply SS Rev. 0.4, ...

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... FUNCTIONAL DESCRIPTION The Fidelix 64Mb SDRAM is a quad-bank DRAM that operates at 1.8V or 2.5V and includes a synchronous inter- face (all signals are registered on the positive edge of the clock signal, CLK ). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...

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CLK CKE /CS /RAS /CAS ADDR BA0 BA1 A10/AP DQ /WE DQM t RP Precharge Auto (All Bank) Refresh Note : 1. The two AUTO REFRESH commands at T4 and T9 may be applied before either ...

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The full-page burst is used in conjunction with the BURST TERMINATE command to gene- rate arbitrary burst lengths. Reserved states should not be used, ...

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Table 2. Burst Length Definition. Burst Length Full Page(y) Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future ...

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CLK Command DQ CLK Command DQ T0 CLK Command Read DQ Rev. 0.4, Aug. ‘ Read NOP Dout t AC CAS Latency Read NOP CAS Latency ...

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Table 3. CAS Latency. Speed 133MHz 100MHz EXTENDED MODE REGISTER The Extended Mode Register controls additional functions such as the Temperature Compensated Self Refresh (TCSR) Control, Partial Array Self Refresh (PASR), Strength.The Extended Mode Register is programmed via the Mode ...

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Table 5. Extended Mode Register Table Note : 11. EM13 and EM12 (BA1 and BA0) ...

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Note : 13. CKE is HIGH for all commands shown except SELF REFRESH and Deep Power Down. 14. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 15. A0-A7 provide column address; A10 HIGH enables the ...

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... RP The addressing is generated by the internal refresh controller. The address bits thus are a “Don’t Care” during an AUTO REFRESH command. The Fidelix 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (t of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed ...

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Maximum Ratings Voltage Supply DD DDQ Relative to V …….…….………………………...-0. 3.6V SS Voltage on Inputs I/O Pins Relative to V …….…….…………………….…. –0.5V to +3.6V SS Storage Temperature(plastic) ………….………. -55℃ 150℃ Power ...

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Table 8. I Specifications and Conditions DD Parameter Operating Current: Active Mode; Burst =2 ; Read or Write ; CAS Latency =3 [28.29.30.] Precharge Standby Current in power down mode : CKE ≤ ...

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AC Characteristics AC Characteristics Parameter [33.] Clock Period Clock High Time Clock Low Time Address Setup Time to Clock Address Hold Time to Clock CKE Setup Time to Clock CKE Hold Time to Clock [34, 35] Clock Access Time Output ...

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AC Characteristics AC Characteristics Parameter Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command Note : 33. The clock frequency must remain constant ...

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Operation BANK / ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command, which selects both the ...

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T0 CLK Command Read Bank Address Col n DQ CAS Latency=1 T0 CLK Command Read Bank Address Col n DQ Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 Rev. ...

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T0 T1 CLK Command Read NOP Bank Address Col n DQ Figure 4. Consecutive Burst Reads -Transition from Burst of 4 Read to a Single read for CAS Latency 1,2,3 T0 CLK Command Read Bank Address Col n DQ Rev. ...

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T0 CLK Command Read Bank Address Col n DQ CAS Latency=2 T0 CLK Command Read Bank Address Col Read Burst can be terminated by a subsequent Write com- mand, and data from a fixed length READ burst ...

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WRITE command that truncated the READ command. The DQM signal must be as- serted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the ...

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T0 CLK DQM Command Read Bank Address Col n DQ CAS Latency CLK CMD Read DQM DQ CMD Read DQM DQ CMD Read DQM DQ Figure 8. Read Interrupted by Write with DQM ; CAS Latency =2 Rev. ...

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A fixed-length READ burst or a full-page burst may be fol- lowed by, or truncated with, a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired ...

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T0 T1 CLK Command Read NOP Bank a Address Col CLK Command Read NOP Bank a Address Col n Dout DQ CAS Latency=1 Rev. 0.4, Aug. ‘ NOP NOP Dout n CAS Latency=3 Figure ...

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T0 T1 CLK Command Read NOP Bank a Address Col n DQ CAS Latency CLK Command Read NOP Bank a Address Col n DQ Rev. 0.4, Aug. ‘ Burst NOP NOP Terminate X=1cycles Dout Dout ...

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CLOCK CKE /CS t RCD /RAS /CAS ADDR RAa CAa BA0 BA1 A10/AP RAa CL=2 t RAC *note 47. DQ CL=3 t RAC *note 47. /WE DQM Row Active Read (A-Bank) (A-Bank) Note : 45. Minimum ...

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CLOCK CKE /CS t RCD /RAS /CAS ADDR RAa CAa BA0 BA1 A10/AP RAa CL=2 t RAC *note 47. DQ CL=3 t RAC *note 47. /WE DQM Row Active Read (A-Bank) (A-Bank) Figure 12. Read & ...

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CLOCK CKE /CS /RAS /CAS ADDR RAa RBb CAa BA0 BA1 A10/AP RAa RBb CL=2 DQ CL=3 /WE DQM Row Active Read (A-Bank) (A-Bank) Row Active (B-Bank) Note : 49. Row precharge will interrupt writing. Last ...

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If auto precharge is enabled, the row being accessed is precharged at the com- pletion of the burst. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE ...

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CLK Command Write Bank Address Col n Din DQ CLK Command Address DQ Figure 16. Write to Write - Transition from a burst single write Data for a fixed-length WRITE burst a full-page WRITE burst may ...

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CLK Command Write Bank Address Col n Din DQ T0 CLK Command Write Bank Address Col n Din DQ n Figure 18. Write to Read Burst of 2 Write and Read(CAS Latency =2) Rev. 0.4, Aug. ‘ Write ...

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T0 CLK >=15ns WR CK DQM Command Write Bank Address Col n Din <=15ns WR CK DQM Command Write Bank Address Col n Din DQ n CLK Command Address DQ Fixed-length or ...

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This is shown in Figure 20. , where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 21 used to deactivate the open row in a particular bank ...

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Precharge Command CLK CKE /CS /RAS /CAS /WE A0-A9,A11 A10 BA0, 1 Rev. 0.4, Aug. ‘07 High All banks Bank Selected Bank Address Don’t Care Figure 21. Precharge Command 36 C(F)MS6416LBx–75Ex ...

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CLK t CKS CKE NOP Command All banks Idle Enter Power Down Mode CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal ...

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T0 CLK CKE Internal CLK NOP Command Address DQ Rev. 0.4, Aug. ‘ Write Bank Col n Din n Figure 23. Clock Suspend During Write Burst 38 C(F)MS6416LBx–75Ex T4 T5 NOP NOP Din Din n+1 n+2 ...

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T0 CLK CKE Internal CLK Read Command Bank Address Col n DQ Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2) Concurrent Auto Precharge If an access command with Auto Precharge is being executed ; ...

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T0 CLK Read-AP Command NOP Bank n Internal States Page Bank n Active Bank m Page Active Bank n Address Col a DQ Figure 25. Read with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 CLK Read-AP NOP Command ...

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T0 CLK Write-AP Command NOP Bank n Internal States Page Bank n Active Bank m Page Active Bank n Address Col a Din DQ Figure 27. Write with Auto Precharge Interrupted by a Read(CAS Latency =3) T0 CLK Write-AP Command ...

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DEEP POWER DOWN MODE ENTRY The Deep Power Down Mode is entered by having burst termination command, while CKE is low. The Deep Power Down Mode has to be maintained for a minimum of 100us. The following diagram illustrates Deep ...

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Table 9. CKE [50.51.52.53.] . CKE CKE n Note : 50. CKE is the logic state of CKE at clock edge n; CKE n 51. Current State is the state of the SDRAM immediately prior to ...

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Table 10. Current State Bank n, Command to Bank n Current State CS# RAS# L Row L Active L L Read(Auto L Precharge L Disabled Write L (Auto Precharge L Disabled) L Table 11. Current State Bank n, ...

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Table 11. Current State Bank n, Command to Bank m Current State CS# RAS# L Read L (With Auto L Precharge Write L (With Auto L Precharge) L Note : 68. This table applies when CKE was HIGH ...

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PACKAGE DIMENSION 54 BALL FINE PITCH BGA Top View # Side View Rev. 0.4, Aug. ‘ ...