AD1859 Analog Devices, AD1859 Datasheet
AD1859
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AD1859 Summary of contents
Page 1
... The analog performance of conventional single bit the sample and master clocks. The AD1859 has a digital Phase Locked Loop (PLL) which allows the master clock to be asyn- chronous, and which also strongly rejects jitter on the sample clock (left/right clock) ...
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... AD1859–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( Ambient Temperature Input Clock (F ) MCLK Input Signal Input Sample Rate Measurement Bandwidth Input Data Word Width Load Capacitance Input Voltage Input Voltage NOTES 2 I S-Justified Mode (Ref. Figure 3). ...
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... MCLK Periods 150 MHz MCP 15 15 Min 4.5 29.5 23.5 Min –40 –55 –3– AD1859 10%) Typ Max Units MHz ns ns Typ Max Units 5 5 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1859 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... I CCLK 19 I CLATCH 21 I –5– AD1859 Description Serial control input, MSB first, containing 8 bits of unsigned data per channel. Used for specifying channel specific attenuation and mute. Control clock input for control data. Control input data must be valid on the rising edge of CCLK ...
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... Power down/reset. The AD1859 is placed in a low power consumption “sleep” mode when this pin is held LO. The AD1859 is reset on the rising edge of this signal. The serial control port registers are reset to their default values. Connect HI for normal operation. ...
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... The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can be configured in left-justified S-justified, right-justified and DSP serial port compatible modes ...
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... A final key advan- tage of analog de-emphasis is that it is sample rate invariant, so that users can fully exploit the sample rate range of the AD1859 and simultaneously use de-emphasis. Digital implementations gen- erally only support fixed, standard sample rates. ...
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... INPUT SDATA LSB MSB MSB-1 MSB-2 INPUT REV. A Note that in 16-bit input mode, the AD1859 is capable BCLK frequency “packed mode” where the MSB is left- S justified to an LRCLK transition, and the LSB is right-justified 2 S-justified mode to an LRCLK transition. LRCLK is HI for the left channel, and LO for the right channel ...
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... Figure 9 shows example connections. The range of audio sample rates (as determined from the LRCLK input) supported by the AD1859 is a function of the master clock rate (i.e., the crystal frequency or external clock source frequency) applied. The highest sample rate supported can be computed as follows: ...
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... Output Drive, Buffering and Loading The AD1859 analog output stage is able to drive load. If lower impedance loads must be driven, an external buffer stage such as the Analog Devices SSM2142 should be used. The ...
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... IDPM0 9 IDPM1 10 Layout and Decoupling Considerations 8 18/16 The recommended decoupling, bypass circuits for the AD1859 are shown in Figure 17. Figure 17 illustrates a connection dia- gram for systems which do not require de-emphasis support. The recommended circuit connection for system including de- emphasis is shown in Figure 18. 20-64pF 20-64pF µ ...
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... PCB and Ground Plane Recommendations The AD1859 ideally should be located above a split ground plane, with the digital pins over the digital ground plane, and the analog pins over the analog ground plane. The split should occur between Pins 6 and 7 and between Pins 22 and 23 as shown in Figure 19 ...
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... FREQUENCY – Hz Figure 26. THD+N vs. Frequency at –0.5 dBFS kHz bandwidth, while the analog performance is specified over kHz bandwidth (i.e., the AD1859 performs slightly better than the plots indicate). Figure 28 shows the power supply rejection performance of the AD1859. The channel separation performance of the AD1859 is shown in Figure 29. The AD1859’ ...
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... AD1859 will reject the left/right clock jitter by virtue of its on-chip digital phase locked loop. Contact Analog Devices Computer Products Division Customer Support at (617) 461-3881 or cpd_support@analog ...
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... AD1859 13 N [12.. [12..0] 13-BIT ADDER 13 + Figure 33. Numerically Controlled Oscillator Circuit 28-Lead Wide-Body SO (R-28) 0.7125 (18.10) 0.6969 (17.70 0.1043 (2.65) PIN 1 0.0926 (2.35) 0.0500 0.020 (0.49) 0.0118 (0.30) SEATING 0.0125 (0.32) (1.27) 0.013 (0.35) 0.0040 (0.10) PLANE BSC 0.0091 (0.23 MHz 13-BIT MSB ADDER BUS RI BUS SELECTOR ...