AD1870 Analog Devices, AD1870 Datasheet - Page 8

• Manufacturer Part Number: AD1870
• Description: Single-Supply 16-Bit Stereo ADC
• Manufacturer: Analog Devices

AD1870
44.1 kHz. The stop band attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. See TPC 7 for the digital filter’s characteristics.
The output from the decimator is available as a single serial
output, multiplexed between left and right channels.
Note that the digital filter itself is operating at 64 × f
consequence, Nyquist images of the passband, transition band,
and stop band will be repeated in the frequency spectrum at
multiples of 64 × f
greater than 90 dB across the frequency spectrum, except for a
window ± 0.55 × f
input signals, clock noise, or digital noise in these frequency
windows will not be attenuated to the full 90 dB. If the high
frequency signals or noise appear within the passband images
within these windows, they will not be attenuated at all, and
therefore input antialias filtering should be applied.
Sample Delay
The sample delay or “group delay” of the AD1870 is dominated
by the processing time of the digital decimation filter. FIR filters
convolve a vector representing time samples of the input with
an equal-sized vector of coefficients. After each convolution, the
input vector is updated by adding a new sample at one end of
the “pipeline” and discarding the oldest input sample at the
other. For a FIR filter, the time at which a step input appears at
the output will be when that step input is half-way through
the input sample vector pipeline. The input sample vector
is updated every 64 × f
group delay for the AD1870 is:
For the most common sample rates this can be summarized as:
Due to the linear phase properties of FIR filters, the group
delay variation, or differences in group delay at different fre-
quencies, is essentially zero.
OPERATING FEATURES
Voltage Reference and External Filter Capacitors
The AD1870 includes a 2.25 V on-board reference that deter-
mines the AD1870’s input range. The left and right reference
pins (14 and 15) should be bypassed with a 0.1 µF ceramic chip
capacitor in parallel with a 4.7 µF tantalum as shown in Figure
3. Note that the chip capacitor should be closest to the pin. The
internal reference can be overpowered by applying an external
reference voltage at the V
allowing multiple AD1870s to be calibrated to the same gain. It
is not possible to overpower the left and right reference pins
individually; the external reference voltage should be applied to
both Pin 14 and Pin 15. Note that the reference pins must still
be bypassed as shown in Figure 3.
While it is possible to bypass each reference pin (V
V
not recommended. A larger capacitor will have a longer charge-
up time, which may extend into the autocalibration period, yield-
ing incorrect results.
REF
R) with a capacitor larger than the suggested 4.7 µF, it is
Group Delay (sec) = 36/f
S
f
48 kHz
44.1 kHz
32 kHz
wide centered at multiples of 64 × f
S
S
. Thus the digital filter will attenuate to
S
REF
. The equation that expresses the
L (Pin 14) and V
Group Delay
750 µs
816 µs
1125 µs
S
(Hz)
REF
R (Pin 15) pins,
REF
S
S
. As a
. Any
L and
The AD1870 requires four external filter capacitors on Pins 11,
12, 17, and 18. These capacitors are used to filter the single-to-
differential converter outputs, and are too large for practical
integration onto the die. They should be 470 pF NPO ceramic
chip type capacitors as shown in Figure 3, placed as close to the
AD1870 package as possible.
Sample Clock
An external master clock supplied to CLKIN (Pin 28) drives
the AD1870 modulator, decimator, and digital interface. As
with any analog-to-digital conversion system, the sampling clock
must be low jitter to prevent conversion errors. If a crystal oscil-
lator is used as the clock source, it should be bypassed with a
0.1 µF capacitor, as shown below in Figure 3.
For the AD1870, the input clock operates at either 256 × f
384 × f
the 384 mode is selected, and when 384/256 is LO, the 256
mode is selected. In both cases, the clock is divided down to
obtain the 64 × f
word rate itself will be at f
popular sample rates below:
256 Mode
CLKIN
12.288 MHz
11.2896 MHz 16.9344 MHz 2.822 MHz
8.192 MHz
The AD1870 serial interface will support both master and slave
modes. Note that in slave mode it is required that the serial
interface clocks be externally derived from a common source.
In master mode, the serial interface clock outputs are internally
derived from CLKIN.
Reset, Autocalibration, and Power-Down
The active LO RESET pin (Pin 23) initializes the digital deci-
mation filter and clears the output data buffer. While in the reset
state, all digital pins defined as outputs of the AD1870 are
driven to ground (except for BCLK, which is driven to the state
defined by RDEDGE (Pin 6)). Analog Devices recommends
resetting the AD1870 on initial power-up so that the device is
properly calibrated. The reset signal must remain LO for the
minimum period specified in “Specifications” above. The reset
pulse is asynchronous with respect to the master clock, CLKIN.
If, however, multiple AD1870s are used in a system, and it is
desired that they leave the reset state at the same time, the
common reset pulse should be made synchronous to CLKIN
(i.e., RESET should be brought HI on a CLKIN falling edge).
Multiple AD1870s can be synchronized to each other by using
a single master clock and a single reset signal to initialize all
devices. On coming out of reset, all AD1870s will begin sam-
pling at the same time. Note that in slave mode, the AD1870 is
inactive (and all outputs are static, including WCLK) until the
first rising edge of LRCK after the first falling edge of LRCK.
This initial low-going then high-going edge of LRCK can be used
to “skew” the sampling start-up time of one AD1870 relative to
other AD1870s in a system. In the Data Position Controlled by
WCLK Input mode, WCLK must be HI with LRCK HI, then
WCLK HI with LRCK LO, then WCLK HI with LRCK HI
before the AD1870 starts sampling.
S
as selected by the 384/256 pin. When 384/256 is HI,
384 Mode
CLKIN
18.432 MHz
12.288 MHz
S
clock required for the modulator. The output
S
. This relationship is illustrated for
Modulator
Sample Rate Rate
3.072 MHz
2.048 MHz
Output Word
48 kHz
44.1 kHz
32 kHz
S
or