AD2S80 Analog Devices, AD2S80 Datasheet - Page 9

• Manufacturer Part Number: AD2S80
• Description: Variable Resolution/ Monolithic Resolver-to-Digital Converter
• Manufacturer: Analog Devices

REV. A
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred af-
ter which the INHIBIT should be returned to a logic “HI” state
to enable the output latches to be updated.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least sig-
nificant byte will be presented on data output DB9 to DB16
(with the ENABLE input taken to a logic “LO”) regardless of
the state of the BYTE SELECT pin. Note that when the
AD2S80A is used with a resolution less than 16 bits the unused
data lines are pulled to a logic “LO.” A logic “HI” on the BYTE
SELECT input will present the eight most significant data bits
on data output DB1 and DB8. A logic “LO” will present the
least significant byte on data outputs 1 to 8, i.e., data outputs 1
to 8 will duplicate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulse width of the ripple clock is 300 ns.
RIPPLE CLOCK is normally set high before a BUSY pulse and
resets before the next positive going edge of the next consecutive
pulse.
The only exception to this is when DIR changes whist the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to pre-
vent false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
–9–
DIRECTION Output
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This corresponds to a change in input rotation
direction but less than 1 LSB.
PARAMETER
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 2. Diode Transistor Logic Nand Gate
ENABLE
SELECT
INHIBIT
INHIBIT
RIPPLE
CLOCK
RIPPLE
CLOCK
DATA
BUSY
DATA
BUSY
DATA
BYTE
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO."
DIR
5k1
T
200
10
470
16
3
70
485
515
–
40
35
60
60
+5V
MIN
V
V
H
H
IN4148
IN4148
V
DIGITAL TIMING
Z
V
t
t
t
V
V
+5V
H
7
t
6
T
600
25
580
45
25
140
625
670
600
110
110
140
125
8
2
L
L
MAX
10k
V
L
t
t
12
t
4
t
V
5
t
V
10
11
H
L
t
1k
1
CONDITION
BUSY WIDTH V
RIPPLE CLOCK V
RIPPLE CLOCK V
BUSY V
BUSY V
INHIBIT V
MIN DIR V
MIN DIR V
INHIBIT V
ENABLE V
ENABLE V
BYTE SELECT V
BYTE SELECT V
t
9
V
V
2N3904
H
L
0V
H
H
V
V
H
L
TO DATA V
TO DATA V
H
L
H
H
L
L
TO DATA STABLE
TO BUSY V
TO DATA V
TO DATA V
TO BUSY V
TO BUSY VH
TO COUNTER
(CLOCK)
V
t
H
13
AD2S80A
t
H
V
L
H
–V
3
H
L
L
TO DATA STABLE
TO DATA STABLE
TO NEXT BUSY V
TO BUSY V
H
H
L
V
V
H
H
L
H
L
H
H
H