EPC16xxx Altera, EPC16xxx Datasheet - Page 18

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Functional Description
Figure 2–5. Clock Divider Unit
2–18
Configuration Handbook, Volume 2
(Up to 133 MHz)
External Clock
f
Programmable Configuration Clock
The configuration clock (DCLK) speed is user programmable. One of two
clock sources can be used to synthesize the configuration clock; a
programmable oscillator or an external clock input pin (EXCLK). The
configuration clock frequency can be further synthesized using the clock
divider circuitry. This clock can be divided by the N counter to generate
your DCLK output. The N divider supports all integer dividers between
1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all
clock divisions other than non-integer divisions is 50% (for the non-
integer dividers, the duty cycle will not be 50%). See
diagram of the clock divider unit.
The DCLK frequency is limited by the maximum DCLK frequency the
FPGA supports.
The maximum DCLK input frequency supported by the FPGA is
specified in the appropriate FPGA family chapter in the Configuration
Handbook.
10 MHz
33 MHz
50 MHz
66 MHz
Internal Oscillator
Configuration Device
Clock Divider Unit
Divide
by N
Figure 2–5
DCLK
Altera Corporation
August 2005
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