EPC16xxx Altera, EPC16xxx Datasheet - Page 6

• Manufacturer Part Number: EPC16xxx
• Description: (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
• Manufacturer: Altera

Functional Description
2–6
Configuration Handbook, Volume 2
f
For detailed information on using these schemes to configure your
Altera FPGA, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
Configuration Signals
Table 2–3
configuration device and Altera FPGAs.
Configuration
DATA[]
DCLK
nINIT_CONF
OE
nCS
Table 2–3. Configuration Signals
Device Pin
Enhanced
lists the configuration signal connections between the enhanced
DATA[]
DCLK
nCONFIG
nSTATUS
CONF_DONE Configuration done output signal driven by the
FPGA Pin
Altera
Configuration data transmitted from the
configuration device to the FPGA, which is latched
on the rising edge of DCLK.
Configuration device generated clock used by the
FPGA to latch configuration data provided on the
DATA[] pins.
Open-drain output from the configuration device
that is used to initiate FPGA reconfiguration using
the initiate configuration (INIT_CONF) JTAG
instruction. This connection is not needed if the
INIT_CONF JTAG instruction is not needed. If
n
nCONFIG must be tied to V
through a pull-up resistor.
Open-drain bidirectional configuration status
signal, which is driven low by either device during
POR and to signal an error during configuration.
Low pulse on OE resets the enhanced
configuration device controller.
FPGA.
INIT_CONF is not connected to nCONFIG,
Description
CC
either directly or
Altera Corporation
August 2005