XC2C64 Xilinx, XC2C64 Datasheet - Page 6

• Manufacturer Part Number: XC2C64
• Description: (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
• Manufacturer: Xilinx

CoolRunner-II CPLD Family
pins.However, if VREF pin placement is not done properly,
additional VREF pins may be required, resulting in a loss of
potential I/O pins or board re-work. See XAPP 399 for
details regarding VREF pins and their placement.
Table 4
and shows which standards require V
termination. V
Table 4: CoolRunner-II CPLD I/O Standard Summary
Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
smallest parts are not banked, so all signals will have the
same output swing for 32 and 64 macrocell parts. The
medium parts (128 and 256 macrocell) support two output
banks. With two, the outputs will switch to one of two
selected output voltage levels, unless both banks are set to
the same voltage. The larger parts (384 and 512 macrocell)
support four output banks split evenly. They can support
groupings of one, two, three or four separate output voltage
levels. This kind of flexibility permits easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V in a single part.
6
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
HSTL-1
SSTL2-1
SSTL3-1
I/O Standard
summarizes the single ended I/O standard support
To Macrocell
REF
Fast Input
detail is given in specific data sheets.
V
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
To AIM
V
Input
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
REF
Open Drain
GTS[0:3]
Disabled
Enabled
Figure 4: CoolRunner-II CPLD I/O Block Diagram
Hysteresis
CGND
REF
CTE
PTB
Board Termination
Voltage (V
values and board
4
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
Available on 128 Macrocell Devices and Larger
From Macrocell
TT
www.xilinx.com
1-800-255-7778
)
V
The Xilinx software aids designers in remaining within the
proper pin range.
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II CPLDs use standard CMOS methods to cre-
ate the CPLD architecture and deliver the corresponding
low current consumption, without doing any special tricks.
However, sometimes designers would like to reduce their
system current even more by selectively disabling circuitry
not being used.
The patented DataGATE technology was developed to per-
mit a straightforward approach to additional power reduc-
tion. Each I/O pin has a series switch that can block the
arrival of free running signals that are not of interest. Sig-
nals that serve no use may increase power consumption,
and can be disabled. Users are free to do their design, then
choose sections to participate in the DataGATE function.
DataGATE is a logic function that drives an assertion rail
threaded
CoolRunner-II CPLD parts. Designers can select inputs to
be blocked under the control of the DataGATE function,
effectively blocking controlled switching signals so they do
not drive internal chip capacitances. Output signals that do
not switch, are held by the bus hold feature. Any set of input
pins can be chosen to participate in the DataGATE function.
Figure 5
quency graph. With DataGATE, designers can approach
zero power, should they choose to, in their designs
Figure 6
pin drives the DataGATE Assertion Rail. It can have any
desired logic function on it. It can be as simple as mapping
an input pin to the DataGATE function or as complex as a
counter or state machine output driving the DataGATE I/O
REF
V CCIO
has pin-range requirements that must be observed.
shows the familiar CMOS I
shows how DataGATE basically works. One I/O
through
V REF
the
Preliminary Product Specification
Global termination
Pullup/Bus-Hold
medium
DS090 (v1.7) October 2, 2003
CC
DS090_04_121201
versus switching fre-
and
high-density
R