XC2V1000-6FG456C Xilinx, XC2V1000-6FG456C Datasheet

no-image

XC2V1000-6FG456C

Manufacturer Part Number
XC2V1000-6FG456C
Description
Field-Programmable Gate Arrays
Manufacturer
Xilinx
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2V1000-6FG456C
Manufacturer:
XILINX
0
DS031-1 (v1.7) October 2, 2001
Summary of Virtex
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
Industry First Platform FPGA Solution
IP-Immersion™ Architecture
-
-
-
SelectRAM™ Memory Hierarchy
-
-
-
Arithmetic Functions
-
-
Flexible Logic Resources
-
-
-
-
-
High-Performance Clock Management Circuitry
-
-
Active Interconnect™ Technology
-
-
SelectI/O-Ultra™ Technology
-
-
-
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities from 40K to 8M system gates
420 MHz internal clock speed (Advance Data)
840+ Mb/s I/O (Advance Data)
3 Mb of True Dual-Port™ RAM in 18-Kbit block
SelectRAM resources
Up to 1.5 Mb of distributed SelectRAM resources
High-performance interfaces to external memory
·
·
·
·
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 93,184 internal registers / latches with Clock
Enable
Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal 3-state bussing
Up to 12 DCM (Digital Clock Manager) modules
·
·
·
16 global clock multiplexer buffers
Fourth generation segmented routing structure
Predictable, fast routing delay, independent of
fanout
Up to 1,108 user I/Os
19 single-ended standards and six differential
standards
Programmable sink current (2 mA to 24 mA) per I/O
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DDR-SDRAM interface
FCRAM interface
QDR™-SRAM interface
Sigma RAM interface
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
®
R
-II Features
0
0
www.xilinx.com
1-800-255-7778
0
Virtex-II 1.5V
Field-Programmable Gate Arrays
Advance Product Specification
-
-
-
-
Supported by Xilinx Foundation™ and Alliance™
Series Development Systems
-
-
-
SRAM-Based In-System Configuration
-
-
-
-
-
-
0.15 µm 8-Layer Metal process with 0.12 µm
high-speed transistors
1.5 V (V
V
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
CCAUX
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
Differential Signaling
·
·
·
·
·
Proprietary high-performance SelectLink™
Technology
·
·
·
Integrated VHDL and Verilog design flows
Compilation of 10M system gates designs
Internet Team Design (ITD) tool
Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
IEEE1532 support
Partial reconfiguration
Unlimited re-programmability
Readback capability
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR Input and Output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
CCINT
auxiliary and V
) core power supply, dedicated 3.3 V
CCO
I/O power supplies
Module 1 of 4
1

Related parts for XC2V1000-6FG456C

XC2V1000-6FG456C Summary of contents

Page 1

... Programmable sink current ( mA) per I/O © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...

Page 2

... The Virtex-II device/package combination table the end of this section) details the maximum number of I/Os for each device and package using wire-bond or flip-chip technology. Table 2: Maximum Number of User I/O Pads Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com 1-800-255-7778 SelectRAM Blocks ...

Page 3

... IOBs support the following single-ended I/O standards: • LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V) • PCI-X at 133 MHz, PCI (3 MHz and 66 MHz) • GTL and GTLP • HSTL (Class I, II, III, and IV) www.xilinx.com 1-800-255-7778 Figure 1, the programmable device is DCM IOB Multiplier DS031_28_100900 elements, ...

Page 4

... Horizontal and vertical routing resources for each row or column include: • 24 long lines bits • 120 hex lines bits • 40 double lines • 16 direct connect lines (total in all four directions) 512 x 36 bits www.xilinx.com 1-800-255-7778 R Virtex™-II Electrical Characteris- DS031-1 (v1.7) October 2, 2001 Advance Product Specification ...

Page 5

... PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, AND RSVD) and VBATT. FG256 FG456 1.00 1. 172 324 FF896 FF1152 1.00 1. 624 824 www.xilinx.com 1-800-255-7778 Table 4 FG676 BG575 BG728 1.00 1. 484 408 FF1517 BF957 1.00 1. ...

Page 6

... Notes: 1. All devices in a particular package are pin-out (footprint) compatible. In addition, the FG456 and FG676 packages are compatible, as are the FF896 and FF1152 packages. Virtex-II Ordering Information Virtex-II ordering information is shown in Example: XC2V1000-5FG456C Device Type Speed Grade (-4, -5, -6) Module Available I/Os ...

Page 7

... DS031-1 (v1.7) October 2, 2001 Advance Product Specification Revision Virtex-II Performance Characteristics sections. • DS031-3, Virtex-II 1.5V FPGAs: Characteristics (Module 3) • DS031-4, Virtex-II 1.5V FPGAs: Functional Description (Module 4) www.xilinx.com 1-800-255-7778 Virtex-II 1.5V Field-Programmable Gate Arrays and Summary of Virtex®-II Features. DC and Switching Pinout Tables Virtex-II Module ...

Related keywords