XC2V1000-6FG456C Xilinx, XC2V1000-6FG456C Datasheet - Page 2

• Manufacturer Part Number: XC2V1000-6FG456C
• Description: Field-Programmable Gate Arrays
• Manufacturer: Xilinx

Virtex-II 1.5V Field-Programmable Gate Arrays
Table 1: Virtex-II Field-Programmable Gate Array Family Members
General Description
The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.
The leading-edge 0.15µm / 0.12µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table
from 40K to 10M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
0.80mm, 1.00mm, and 1.27mm pitches. In addition to tradi-
tional wire-bond interconnects, flip-chip interconnect is used
in some of the BGA offerings. The use of flip-chip intercon-
nect offers more I/Os than is possible in wire-bond versions
of the similar packages. Flip-Chip construction offers the
combination of high pin count with high thermal capacity.
Module 1 of 4
2
Notes:
1.
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Device
See details in
1, the Virtex-II family comprises 12 members, ranging
System
Gates
250K
500K
Table 2, “Maximum Number of User I/O
1.5M
40K
80K
1M
2M
3M
4M
6M
8M
Row x Col.
112 x 104
(1 CLB = 4 slices = Max 128 bits)
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
16 x 8
Array
8 x 8
10,752
14,336
23,040
33,792
46,592
Slices
1,536
3,072
5,120
7,680
256
512
CLB
Distributed
RAM Kbits
Maximum
www.xilinx.com
1-800-255-7778
1,056
1,456
160
240
336
448
720
16
48
96
8
Pads”.
Table 2
The Virtex-II device/package combination table
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.
Table 2: Maximum Number of User I/O Pads
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Multiplier
Blocks
120
144
168
24
32
40
48
56
96
Device
4
8
shows the maximum number of user I/Os available.
18-Kbit
Blocks
SelectRAM Blocks
120
144
168
24
32
40
48
56
96
4
8
Wire-Bond
Max RAM
(Kbits)
120
200
264
328
392
456
516
Advance Product Specification
1,008
1,728
2,160
2,592
3,024
88
DS031-1 (v1.7) October 2, 2001
144
432
576
720
864
72
DCMs
12
12
12
12
4
4
8
8
8
8
8
Flip-Chip
1,104
1,108
432
528
624
720
912
(Table 6
Max I/O
Pads
1,104
1,108
120
200
264
432
528
624
720
912
88
(1)
at
R