XC2VPX70 Xilinx, XC2VPX70 Datasheet - Page 20

• Manufacturer Part Number: XC2VPX70
• Description: (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: Xilinx

DS123 (v2.9) May 09, 2006
TMS
TDO
TCK
TDI
V
CCJ
Revision
Control
Design
Logic
V
CCO
R
V
CCINT
Figure 12: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
Notes
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT
4. For the XCFxxP the CF pin is a bidirectional pin.
CCINT
CCO
CCJ
External
Oscillator
EN_EXT_SEL
REV_SEL[1:0]
DONE
CF / PROG_B
signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used,
then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to V
must be tied to V
(2)
(2)
(3)
OE/RESET
CLK
CF
CEO
TDO
CE
D0
(3)
(4)
CCO
via a 4.7 kΩ pull-up resistor.
V
CCJ
V
CCO
V
CCINT
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
CCINT
CCO
CCJ
For the XCFxxP, if CF is not connected to PROGB, then it
(2)
(2)
OE/RESET
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Platform Flash In-System Programmable Configuration PROMS
CCO
CLK
CF
.
CEO
TDO
CE
D0
(3)
(4)
V
CCO
(2)
(1)
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
Xilinx FPGA
Slave Serial
MODE PINS
DOUT
(1)
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
Xilinx FPGA
Slave Serial
MODE PINS
ds123_17_122105
TDO
(1)
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