MT9075B Mitel Networks Corporation, MT9075B Datasheet - Page 21

• Manufacturer Part Number: MT9075B
• Description: E1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Preliminary Information
The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 9).
When the C4b and the E2o clocks are not phase-
locked, the rate at which data is being written into the
slip buffer from the PCM 30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip buffer
will perform a controlled frame slip. That is, the buffer
pointers will be automatically adjusted so that a full
PCM 30 frame is either repeated or lost. All frame
slips occur on PCM 30 frame boundaries.
Two status bits, RSLIP and RSLPD (page 03H,
address 15H), give indication of a slip occurrence
and direction. RSLIP changes state in the event of a
slip. If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, a underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.
Figure 9 illustrates the relationship between the read
and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer
Conversely, if the read pointer moves more than 60
channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 channels peak (26 channels peak-to-peak) or a
wander tolerance of 208 UI.
Read Pointer
47 CH
Read Pointer
34
60 CH
34 CH
channels
512 Bit
Elastic
Store
Write Pointer
from
Figure 9 - Read and Write Pointers in the Slip Buffers
28 CH
2 CH
the
Read Pointer
Read Pointer
write
15 CH
pointer.
-13 CH
13 CH
Framing Algorithm
The MT9075B contains three distinct framing
algorithms:
multiframe
alignment. Figure 10 is a state diagram that
illustrates these algorithms and how they interact.
After power-up, the basic frame alignment framer will
search for a frame alignment signal (FAS) in the PCM
30 receive bit stream. Once the FAS is detected, the
corresponding bit 2 of the non-frame alignment
signal (NFAS) is checked. If bit 2 of the NFAS is zero
a new search for basic frame alignment is initiated. If
bit 2 of the NFAS is one and the next FAS is correct,
the
synchronization has been found (i.e., page 03H,
address 10H, bit 7, SYNC is zero).
Once basic frame alignment is acquired the
signalling and CRC-4 multiframe searches will be
initiated. The signalling multiframe algorithm will
align to the first multiframe alignment signal pattern
(MFAS = 0000) it receives in the most significant
nibble of channel 16 (page 3, address 10H, bit 6,
MFSYNC = 0). Signalling multiframing will be lost
when two consecutive multiframes are received in
error.
The CRC-4 multiframe alignment signal is a 001011
bit sequence that appears in PCM 30 bit position one
of the NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table
7). In order to achieve CRC-4 synchronization two
CRC-4 multiframe alignment signals must be
received without error (page 03H, address 10H, bit 5,
CRCSYN = 0) within 8 msec.
algorithm
alignment
basic
declares
frame
and
Wander Tolerance
alignment,
that
CRC-4
MT9075B
basic
multiframe
signalling
frame
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