MT9162 MITEL, MT9162 Datasheet - Page 2

• Manufacturer Part Number: MT9162
• Description: ISO2-CMOS 5 Volt Single Rail Codec
• Manufacturer: MITEL

MT9162
Pin Description
7-162
Pin #
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions.
PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).
RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal
TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal
AOUT+ Non-Inverting Analog Output. (balanced).
AOUT-
Name
CSL0
CSL1
CSL2
V
STB
Ain+
V
D
V
V
Ain-
A/
D
IC
Bias
Ref
DD
out
SS
in
Bias Voltage (Output). (V
Connect 0.1
Reference Voltage for Codec (Output). Nominally [(V
Connect 0.1
Internal Connection. Tie externally to V
A/ Law Selection. CMOS level compatable input pin governs the companding law used by
the device. A-law selected when pin tied to V
operation. CMOS level compatible.
operation. CMOS level compatible.
Clock Speed Select. These pins are used to program the speed of the SSI mode as well as
the conversion rate between the externally supplied MCL clock and the 512 kHz clock required
by the filter/codec. Refer to Table 2 for details. CMOS level compatible.
Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.
Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the
falling edge of BCL during the timeslot defined by STB. CMOS level compatible.
Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and
receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.
Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatible.
Positive Power Supply. Nominally 5 volts.
Inverting Analog Output. (balanced).
Ground. Nominally 0 volts.
Inverting Analog Input. No external anti-aliasing is required.
Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.
F capacitor to V
F capacitor to V
RXMUTE
TXMUTE
PWRST
VBias
CSL0
CSL1
CSL2
VRef
20 PIN PDIP/SOIC/SSOP
A/
IC
Figure 2 - Pin Connections
DD
10
1
2
3
4
5
6
7
8
9
/2) volts is available at this pin for biasing external amplifiers.
SS
SS
. Connect 1 F capacitor to VBias
. Connect 1 F capacitor to Vref.
Description
20
19
18
17
16
15
14
13
12
11
SS
for normal operation.
DD
AIN+
AIN-
VSS
VDD
CLOCKin
STB
Din
Dout
AOUT +
AOUT -
or -law selected when pin tied to V
DD
/2)-1.9] volts. Used internally.
Advance Information
SS
.