MT8950 Mitel Networks Corporation, MT8950 Datasheet - Page 9

• Manufacturer Part Number: MT8950
• Description: ISO-CMOS ST-BUS FAMILY Data Codec
• Manufacturer: Mitel Networks Corporation

for transmission out on the ST-BUS output pin
(DSTo).
functionally disconnected from the input circuitry.
The outputs (pins 18 and 19) are in a non-active
state, i.e., D
HIGH.
Mode 5: Data Loopback - Local Violation Word.
This mode can be used for testing the operation of
the chip in the local carrier mode. The Violation word
is generated as in the local carrier mode. However,
the modulated signal is not output on D
rerouted to the NRZ/RZ input circuit, encoded into
the TEM format and output on DSTo.
Mode 6: Normal Mode - Drive Point Activated.
The drive point output (Pin 14) is set HIGH in this
mode. The codec operation is normal in every other
respect. This drive point can be used to control
external circuitry.
operation is changed.
Mode 7: Idle. In the idle mode D
are in a non-active state, i.e., D
and D
input circuitry operates normally.
Device Monitoring Features
There are two output pins which can be used to
monitor the codec.
D
Output
(RZ
Mode)
D
Output
(NRZ
Mode)
R
R
2
CRB = Control Register Bit
2
R
2 is steady HIGH. The encoder stage and the
The NRZ/RZ inputs (Pins 9 and 10) are
Figure 6 - Violation Word Timing in the Local Carrier Mode for a 600Hz input to SCLK
SYNCH
R
1 is steady LOW and D
SYNCH
6.7 ± 0.83 msec
Note: The polarity of this output can be inverted - depending on the state of the last transition.
It is reset when the mode of
b0
CRB2
b1
R
R
b2 b3
1 and D
1 is steady LOW
msec
1.67
b0
R
2 is steady
CRB3
R
b4
R
2 outputs
0=1.67 msec
1=3.33 msec
2.
CRB2
b1
CRB4
It is
b5
b6
1. Data Activity (DA): This output goes from high
2. Scan Point output (SPo):
msec
1.67
b2
to low when a SPACE signal, indicating the
beginning of data activity, is received by the NRZ/
RZ input circuitry. The level on this pin is reset by
setting bit 1 of the Control Register to logic “1”.
LOW whenever SPi input undergoes a low to high
transition. It is reset by a logic “1” in bit 0 of the
Control Register. The SPi input is generally used
in conjunction with pin 11 to detect a long SPACE
condition in the data.
required to utilize this feature is illustrated in
Figure 7. Note that Pin 11 (NRZo) is an open
drain output.
codec is converted to the NRZ format and output
on this pin. The RC time constant for the circuit
shown in Figure 7 can be set to detect SPACE
conditions of varying time durations. The length
of the long SPACE detected is given by
Where T
milliseconds.
generated when the BREAK key on a data
terminal is depressed.
value of R equal to 210 k
can be used.
SYNCH
msec
1.67
b3
SP
0=1.67 msec
1=3.33 msec
b0
is the duration of the SPACE in
CRB3
b4
ISO-CMOS
CRB2
The NRZ/RZ data input to the
A long SPACE of 150ms is
b1
T
SP
=0.7RC
35 s Nominal
b2 b3
0=1.67 msec
1=3.33 msec
To detect this signal, a
CRB4
The external circuitry
b5
and C equal to 1.0µF
CRB3
This output is set
b4
MT8950
msec
1.67
CRB4
b6
b5
SYNCH
b6
6-11