MT8976 Mitel Networks Corporation, MT8976 Datasheet - Page 15

• Manufacturer Part Number: MT8976
• Description: ISO-CMOS ST-BUS FAMILY T1/ESF Framer Circuit
• Manufacturer: Mitel Networks Corporation

Framing Algorithm
In ESF mode, the framer searches for a correct FPS
pattern. Figure 8 shows a state diagram of the
framing algorithm. The dotted lines show which
feature can be switched in and out depending upon
the operating mode of the device.
When the device is operating in the D3/D4 format,
the framer searches for the F
repeating 1010... pattern in a specific bit position
every alternate frame. It will synchronize to this
pattern
synchronization by clearing bit 0 in Master Status
Word 1. The device will subsequently initiate a
search for the F
frames (see Table 4). When a correct F
been located, bit 3 in Master Status Word 1 is
cleared indicating that the device has achieved
multiframe synchronization.
Note: the device will remain in terminal frame syn-
chronization even if no F
In D3/D4 format, when the CRC/MIMIC bit in Master
Control Word 1 is cleared, the device will not go into
synchronization if more than one bit position in the
frame has a repeating 1010.... pattern, i.e., if more
than one candidate for the terminal framing position
is located. The framer will continue to search until
only one terminal framing pattern candidate is
discovered. It is, therefore, possible that the device
may not synchronize at all in the presence of PCM
code sequences (e.g., sequences generated by
some types of test signals), which contain mimics of
the terminal framing pattern.
Setting CRC/MIMIC bit high will force the framer to
synchronize to the first terminal framing pattern
detected. In standard D3/D4 applications, the user’s
system software should monitor the multiframe
synchronization state indicated by bit 3 in Master
Status Word 1. Failure of the device to achieve
multiframe synchronization within 4.5ms of terminal
frame synchronization, is an indication that the
device has framed up to a terminal framing pattern
mimic and should be forced to reframe.
One of the main features of the framer is that it
performs its function "off line". That is, the framer
repositions the receive circuit only when it has
detected a valid frame position. When the framer
exits maintenance mode the receive counters remain
where they are until the framer has found a new
frame position. This means that if the user forces a
reframe when the device was really in the right
place, there will not be any disturbance in the circuit
and
declare
S
pattern to locate the signalling
S
pattern can be located.
valid
T
terminal
pattern, i.e., a
S
pattern has
frame
because the framer has no effect on the receiver
until it has found synchronization. The out of
synchronization criterion can be controlled by bit 0 in
Master Control Word 2. This bit changes the out of
frame conditions for the maintenance state.
The out of sync threshhold can be changed from 2
out of 4 errors in F
F
ESF mode, and 12ms for D3/D4 modes.
Figure 9 is a bar graph which shows the probability
of achieving frame synchronization at a specific time.
The chart shows the results for ESF mode with CRC
check, and D3/D4 modes of operation. The average
reframe time with random data is 24 ms for ESF, and
13 msec. D3/D4 modes. The probability of a reframe
time of 35 ms or less is 88% for ESF mode, and
97% for D3/D4 modes. In ESF mode it is
recommended that the CRC check be enabled
unless the line has a high error rate. With the CRC
check disabled the average reframe time is greater
because the framer must also check for mimics.
Applications
Figure 10 shows the external components that are
required in a typical ESF application. The MT8980 is
used to control and monitor the device as well as
switch data to DSTi and DSTo. The MT8952, the
HDLC protocol controller, is shown in this application
to illustrate how the data on the FDL could be used.
The digital phase-locked loop, the
provides
functional interface. The clock input to the MT8976
at E1.5i is extracted from the received data signal
with an external circuit. The E1.5i clock is internally
divided by 193 to obtain an 8 kHz clock, which is
output at E8Ko. The MT8940/41 uses this 8 kHz
signal to provide a phase locked 2.048 MHz clock for
the ST-BUS interface and a 1.544 MHz clock for the
DS1 transmit side. Using the 8 kHz signal as a
reference for the MT8940/41 DPLL effectively filters
out the high frequency jitter in the extracted clock.
Thus the C2 and C1.5 clocks generated by the
MT8940/41 will have significantly lower jitter than
would be the case if the extracted 1.5 MHz clock was
used as a reference directly.
An external line driver circuit is required in order to
interface the device to twisted pair cabling. The split
phase unipolar signals output by the MT8976 at TxA
and TxB are used by the line driver circuit to
generate a bipolar AMI signal. The line driver is
transformer coupled to an equalization circuit and
the DS1 line. Equalization of the transmitted signal is
required to meet the specifications for crossconnect
T
(or FPS). The average reframe time is 24 ms for
all
the
T
ISO-CMOS
clocks
(or FPS) to 4 out of 12 errors in
necessary to make a
MT8976
MT8940/41,
4-43