L320MT90QI Advanced Micro Devices, L320MT90QI Datasheet - Page 12

• Manufacturer Part Number: L320MT90QI
• Description: 32 Megabit 2 M X 16-bit/4 M X 8-bit Mirrorbit 3.0 Volt-only Boot Sector Flash Memory - Advanced Micro Devices
• Manufacturer: Advanced Micro Devices

If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
12
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DC Characteristics
DC Characteristics
Sector Address
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
011000xxx
011001xxx
011010xxx
000111xxx
001111xxx
010111xxx
011011xxx
A20–A12
Table 2. Am29LV320MT Top Boot Sector Architecture
table for the automatic
table for the standby
(Kbytes/Kwords)
Sector Size
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
D A T A S H E E T
RP
Am29LV320MT/B
ACC
, the
+
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0E0000h–0EFFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
080000h–08FFFFh
090000h–09FFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
180000h–18FFFFh
190000h–19FFFFh
070000h–07FFFFh
170000h–17FFFFh
110000h–11FFFFh
Address Range
IL
but not within V
(x8)
AC Characteristics
SS
±0.3 V, the standby current will
IH
, output from the device is
CC4
tables for RESET# pa-
A8000h–AFFFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
A0000h–A7FFFh
B0000h–B7FFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
Address Range
SS
). If RESET# is held
±0.3 V, the device
(x16)
May 16, 2003