SSTV16859 Fairchild Semiconductor, SSTV16859 Datasheet

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SSTV16859

Manufacturer Part Number
SSTV16859
Description
Dual Output 13-Bit Register
Manufacturer
Fairchild Semiconductor
Datasheet

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www.DataSheet4U.com
© 2002 Fairchild Semiconductor Corporation
SSTV16859G
(Note 1)(Note 2)
SSTV16859MTD
(Note 2)
SSTV16859
Dual Output 13-Bit Register with
SSTL-2 Compatible I/O and Reset
General Description
The SSTV16859 is a dual output 13-bit register designed
for use with 184 and 232 pin DDR-1 memory modules. The
device has a differential input clock, SSTL-2 compatible
data inputs and a LVCMOS compatible RESET input. The
device has been designed to meet the JEDEC DDR mod-
ule register specifications.
The device has been fabricated on an advanced sub-
micron CMOS process and is designed to operate at power
supplies of less than 3.6V’s.
Ordering Code:
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
BGA96A
MTD64
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500414
Features
I Compliant with DDR-I registered module specifications
I Operates at 2.5V ± 0.2V V
I SSTL-2 compatible input structure
I SSTL-2 compliant output structure
I Differential SSTL-2 compatible clock inputs
I Low power mode when device is reset
I Industry standard 64 pin TSSOP package
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Package Description
DD
March 2001
Revised July 2002
www.fairchildsemi.com

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SSTV16859 Summary of contents

Page 1

... SSTL-2 Compatible I/O and Reset General Description www.DataSheet4U.com The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR mod- ule register specifications ...

Page 2

Connection Diagrams www.DataSheet4U.com www.fairchildsemi.com Pin Descriptions Pin Name Pin Assignment for TSSOP RESET REF V DDQ FBGA Pin Assignments Pin Assignment for FBGA Truth Table RESET L = ...

Page 3

... The SSTL-2 data inputs transition based on the value stable system reference used for setting REF REF the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the V signal. REF ...

Page 4

Absolute Maximum Ratings Supply Voltage (V Supply Voltage (V Reference Voltage (V Input Voltage (V Output Voltage (V Outputs Active (Note 4) DC Input Diode Current (I < > www.DataSheet4U.com DC Output Diode ...

Page 5

DC Electrical Characteristics Symbol R Output HIGH On Resistance OH R Output LOW On Resistance ∆ Electrical Characteristics Symbol www.DataSheet4U.com f Maximum Clock Frequency MAX t Pulse Duration, CK, CK HIGH ...

Page 6

AC Loading and Waveforms Note: C includes probe and jog capacitance L www.DataSheet4U.com Note: I tested with clock and data inputs held mA. and I O FIGURE 3. Voltage and Current Waveforms Inputs FIGURE 5. ...

Page 7

Physical Dimensions www.DataSheet4U.com inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions www.DataSheet4U.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY ...

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