MC145170-1 Motorola, MC145170-1 Datasheet - Page 16

• Manufacturer Part Number: MC145170-1
• Description: PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE
• Manufacturer: Motorola

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DataSheet
4
MC145170–1
16
U
NOTE:
DEFINITIONS:
RECOMMENDED READING:
For a nominal design starting point, the user might consider a damping factor
f R is the frequency at the phase detector input. Larger n values result in faster loop lock times and, for similar sideband filtering, higher
f R –related VCO sidebands.
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Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook , Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN . March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992.
K VCO (VCO Gain) =
For (C), R 1 is frequently split into two series resistors; each resistor is equal to R 1 divided by 2. A capacitor C C is then placed from the
midpoint to ground to further filter the error pulses. The value of C C should be such that the corner frequency of this network does not
significantly affect n .
1987.
N = Total Division Ratio in Feedback Loop
K (Phase Detector Gain) = V DD / 4 V/radian for PD out
K (Phase Detector Gain) = V DD / 2 V/radian for V and R
(A)
(B)
(C)
R
V
PD out
PD out
2
V VCO
R 1
R 1
f VCO
C
C
R 1
R 1
C
R 2
PHASE–LOCKED LOOP — LOW PASS FILTER DESIGN
VCO
R 2
VCO
–
+
R 2
A
C
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VCO
0.7 and a natural loop frequency n
F(s) =
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
n =
n =
n =
=
=
=
0.5 n
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(R 1 + R 2 )sC + 1
2K K VCO
R 2 sC + 1
R 1 sC + 1
n R 2 C
R 1 sC
N n
2
K K VCO
NC(R 1 + R 2 )
R 2 sC + 1
K K VCO
1
NR 1 C
K K VCO
NCR 1
R 2 C +
K K VCO
N
(2 f R /50) where
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