MC145170-1 Motorola, MC145170-1 Datasheet - Page 9

• Manufacturer Part Number: MC145170-1
• Description: PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE
• Manufacturer: Motorola

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OSC in . A 0.01 F coupling capacitor is used for measure-
ment purposes and is the minimum size recommended for
applications. An external feedback resistor of approximately
10 M
the ac–coupled case (see Figure 8). OSC out is an internal
node on the device and should not be used to drive any loads
(i.e., OSC out is unbuffered). However, the buffered REF out
is available to drive external loads.
maximum frequencies are given in the Loop Specifications
table. These maximum frequencies apply for R Counter
divide ratios as indicated in the table. For very small ratios,
the maximum frequency is limited to the divide ratio times
2 MHz. (Reason: the phase/frequency detectors are limited
to a maximum input frequency of 2 MHz.)
(V DD to V SS ), then dc coupling can be used. In the dc–
coupled case, no external feedback resistor is needed.
OSC out must be a No Connect to avoid loading an internal
node on the device, as noted above. For frequencies below
1 MHz, dc coupling must be used. The R counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the OSC in pin. See Figure 22.
decrement by one.
REF out
Reference Frequency Output (Pin 3)
reference frequency or externally provided reference source.
This output may be enabled, disabled, or scaled via bits in
the C register (see Figure 14).
thereby saving a crystal. Upon power up, the on–chip
power–on–initialize circuit forces REF out to the OSC in
divided–by–8 mode.
Specifications table. Therefore, divide values for the refer-
ence divider are restricted to two or higher for OSC in fre-
quencies above 10 MHz.
via the C register to minimize dynamic power consumption
and electromagnetic interference (EMI).
COUNTER OUTPUT PINS
f R
R Counter Output (Pin 9)
er. f R can be enabled or disabled via the C register (pat-
ented). The output is disabled (static low logic level) upon
power up. If unused, the output should be left disabled and
unconnected to minimize interference with external circuitry.
ratio. This ratio extends from 5 to 32,767 and is determined
by the binary value loaded into the R register. Also, direct
access to the phase detector via the OSC in pin is allowed by
choosing a divide value of 1 (see Figure 15). The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of f R must not exceed 2 MHz.
pulses high.
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If desired, an external clock source can be ac coupled to
The external signal level must be at least 1 V p–p; the
If an external source is available which swings rail–to–rail
Each rising edge on the OSC in pin causes the R counter to
This output is the buffered output of the crystal–generated
REF out can be used to drive a microprocessor clock input,
REF out is capable of operation to 10 MHz; see the Loop
If unused, the pin should be floated and should be disabled
This signal is the buffered output of the 15–stage R count-
The f R signal can be used to verify the R counter’s divide
When activated, the f R signal appears as normally low and
is required across the OSC in and OSC out pins in
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f V
N Counter Output (Pin 10)
er. f V can be enabled or disabled via the C register (pat-
ented). The output is disabled (static low logic level) upon
power up. If unused, the output should be left disabled and
unconnected to minimize interference with external circuitry.
ratio. This ratio extends from 40 to 65,535 and is determined
by the binary value loaded into the N register. The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of f V must not exceed 2 MHz.
pulses high.
LOOP PINS
f in
Frequency Input (Pin 4)
the on–chip amplifier which drives the N counter. This signal
is normally sourced from an external voltage–controlled os-
cillator (VCO), and is ac–coupled into f in . A 100 pF coupling
capacitor is used for measurement purposes and is the mini-
mum size recommended for applications (see Figure 7). The
frequency capability of this input is dependent on the supply
voltage as listed in the Loop Specifications table. For small
divide ratios, the maximum frequency is limited to the divide
ratio times 2 MHz. (Reason: the phase/frequency detectors
are limited to a maximum frequency of 2 MHz.)
listed in the Electrical Characteristics table, dc coupling
may be used. Also, for low frequency signals (less than the
minimum frequencies shown in the Loop Specifications
table), dc coupling is a requirement. The N counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the f in pin. See Figure 22.
decrement by 1.
PD out
Single–Ended Phase/Frequency Detector Output
(Pin 13)
when combined with an external low–pass filter. Through use
of a Motorola patented technique, the detector’s dead zone
has been eliminated. Therefore, the phase/frequency detec-
tor is characterized by a linear transfer function. The opera-
tion of the phase/frequency detector is described below and
is shown in Figure 17.
pulses from high impedance
pulses from high impedance
dance state; voltage at pin determined by loop filter
pulses from high impedance
pulses from high impedance
dance state; voltage at pin determined by loop filter
This signal is the buffered output of the 16–stage N count-
The f V signal can be used to verify the N counter’s divide
When activated, the f V signal appears as normally low and
This pin is a frequency input from the VCO. This pin feeds
For signals which swing from at least the V IL to V IH levels
Each rising edge on the f in pin causes the N counter to
This is a three–state output for use as a loop error signal
POL bit (C7) in the C register = low (see Figure 14)
Frequency of f V > f R or Phase of f V Leading f R : negative
Frequency of f V < f R or Phase of f V Lagging f R : positive
Frequency and Phase of f V = f R : essentially high–impe–
POL bit (C7) = high
Frequency of f V > f R or Phase of f V Leading f R : positive
Frequency of f V < f R or Phase of f V Lagging f R : negative
Frequency and Phase of f V = f R : essentially high–impe–
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MC145170–1
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