TA2024C Tripath Technology Inc., TA2024C Datasheet - Page 4

• Manufacturer Part Number: TA2024C
• Description: Stereo 15w 4 ? Class-t ?igital Audio Amplifier Using Digital Power Processing ?echnology
• Manufacturer: Tripath Technology Inc.

P I N D E S C R I P T I O N
T A 2 0 2 4 C P I N O U T
4
24, 27;
25, 26,
13, 21,
23, 32,
10, 14
11, 15
20, 35
31, 28
29, 30
5, 8,
2, 3
4, 9
Pin
17
12
16
18
19
22
34
33
36
6
7
1
OAOUT1, OAOUT2
OUTP2 & OUTM2;
OUTP1 & OUTM1
AGND1, AGND2,
PGND2, PGND1
DCAP2, DCAP1
OVERLOADB
VDD2, VDD2
VDD1, VDD1
INV1, INV2
V5D, V5A
BIASCAP
Function
CPUMP
AGND3
5VGEN
SLEEP
FAULT
DGND
MUTE
VDDA
REF
NC
OVERLOADB
BIASCAP
OAOUT1
OAOUT2
+5VGEN
AGND1
AGND2
AGND3
DCAP2
DCAP1
SLEEP
MUTE
INV1
INV2
V5D
REF
V5A
NC
Input stage bias voltage (approximately 2.4VDC).
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Analog Ground
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used. Unlike previous
Tripath devices, the input bias is still active, even if the MUTE pin is tied to a logic
high.
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground. Connect to AGND locally (near the TA2024C).
Bridged output pairs
Supply pins for high current H-bridges, nominally 12VDC.
Not connected. Not bonded internally.
Analog 12VDC
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
36-pin Power SOP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
(Top View)
T r i p a t h T e c h n o l o g y , I n c . - T e c h n i c a l I n f o r m a t i o n
Description
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
CPUMP
PGND1
NC
VDDA
NC
OUTP1
VDD1
VDD1
OUTM1
OUTM2
VDD2
VDD2
OUTP2
NC
DGND
NC
PGND2
FAULT
TA2024C –KL/1.0/01.06