ISL12029 Intersil Corporation, ISL12029 Datasheet - Page 18
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ISL12029
Manufacturer Part Number
ISL12029
Description
Real Time Clock/Calendar
Manufacturer
Intersil Corporation
Datasheet
1.ISL12029.pdf
(28 pages)
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Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first four bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation. Refer
to Figure 19.
After loading the entire Slave Address Byte from the SDA
bus, the ISL12029 compares the device identifier and device
Array
CCR
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
DATA OUTPUT
SCL FROM
MASTER
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
A7
1
1
D7
0
DEVICE IDENTIFIER
18
A6
0
1
D6
0
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
A5
D5
1
0
0
A4
D4
0
1
0
1
A3
D3
1
0
ISL12029
A2
D2
1
0
select bits with ‘1010111’ or ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the SDA
line.
Following the Slave Byte is a two byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power up the internal
address counter is set to address 0h, so a current address
read of the EEPROM array starts at address 0. When
required, as part of a random read, the master must supply
the 2 Word Address Bytes as shown in Figure 19.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
A1
D1
1
0
R/W
A8
A0
D0
8
ACKNOWLEDGE
SLAVE ADDRESS BYTE
WORD ADDRESS 1
WORD ADDRESS 0
DATA BYTE
9
BYTE 0
BYTE 3
BYTE 1
BYTE 2
April 17, 2006
FN6206.4