ISL21400 Intersil Corporation, ISL21400 Datasheet
ISL21400
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ISL21400 Summary of contents
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... Data Sheet Programmable Temperature Slope Voltage Reference The ISL21400 features a precision voltage reference combined with a temperature sensor whose output voltage varies linearly with temperature. The precision 1.20V reference has a very low temperature coefficient (tempco), and its output voltage is scaled by an internal DAC (V produce a temperature stable output voltage that is programmable from ...
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... SDA 7 VOUT Block Diagram BIAS 255 255 2 ISL21400 2 Hardwire slave address pin for I C serial bus 2 Hardwire slave address pin for I C serial bus 2 Hardwire slave address pin for I C serial bus Ground pin Serial bus clock input ...
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... Temperature Slope Non-Linearity DNL DAC Relative Linearity (V =2.7 to 5.5V INL DAC Absolute Linearity (V = 2.7 to 5.5V ISL21400 Thermal Information Thermal Resistance (Typical, Note 15 MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . CC Moisture Sensitivity for MSOP Package +0.3V (See Technical Brief TB363 Level 2 CC Maximum Junction Temperature (Plastic Package +150°C Recommended Operating Conditions Temperature .-40° ...
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... IH Hysteresis SDA and SCL Input Buffer Hysteresis V SDA Output Buffer LOW Voltage OL C Pin Capacitance pin f SCL Frequency SCL 4 ISL21400 = 25°C to +85°C, unless otherwise noted A TEST CONDITIONS (Notes 255 128 +25° 5. 255 128 +25° ...
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... DH t SDA and SCL Rise Time R t SDA and SCL Fall Time F Cb Capacitive Loading of SDA or SCL 5 ISL21400 TEST CONDITIONS MIN Any pulse narrower than the max spec is suppressed (Note 3) SCL falling edge crossing 30 until SDA exits CC the 30 ...
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... --------- - = OUT V REF 255 ⎩ 2. Typical values are for T = +25°C and ISL21400 TEST CONDITIONS Maximum is determined and t F For Cb = 400pF, max is about 2~2.5kΩ For Cb = 40pF, max is about 15~20kΩ = GND to V OUT 100µA (Note 3), at 3mA ...
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... See Tech Brief TB379 for details. JA Typical Performance Curves 3 2.5 2 127 1 1 0.5 0.0 -40 - TEMPERATURE (°C) FIGURE TEMPERATURE (A OUT 7 ISL21400 , Tmin – Tmax OUT OUT TS ------------------------------------------------------------------------------- - = Tmin Tmax – DC 1.20V 255 255 REF ( ) V V measured – ...
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... OUT FIGURE 5. V VOLTAGE NOISE (A OUT 1.22 1.21 1.20 1.19 VREF REGISTER = 255d TS REGISTER = 127d 1.18 -40 - TEMPERATURE (°C) FIGURE 7. ACCURACY vs TEMPERATURE (-40°C TO +85°C) 8 ISL21400 (Continued) 4.5 5.0 5.5 6.0 FIGURE 4. SUPPLY VOLTAGE vs SUPPLY CURRENT = 1, NO LOAD) FIGURE 0.4 VREF REGISTER = 255d +85°C TS REGISTER = 127d 0.35 0.3 0.25 0.2 -40× ...
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... VREF REGISTER = 255d 1.208 TS REGISTER = 127d At +25°C 1.207 1.206 1.205 1.204 1.203 1.202 1.201 1 (mA) OUT FIGURE 13 OUT OUT 9 ISL21400 (Continued) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1. 105 120 135 15 0 165 180 195 210 225 240 255 CODE (m) FIGURE 12 ...
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... DACs can determine the output voltage as defined by Equation 1 (See Register Information). Output Gain Amplifier Section The ISL21400 contains an output gain amplifier (A) that is programmed via the I last stage before the output and therefore controls the overall gain for the device. The gain can be programmed for 1x, 2x amplification ...
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... Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 10). On power-up of the ISL21400 the SDA pin is in the input mode. 2 All I ...
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... A valid Identification Byte contains 0101 the seven MSBs. The bits must correspond to the logic levels at those pins of the ISL21400 device. The LSB in the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (See Table 4) Write Operation TABLE 4 ...
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... FROM THE A IDENTIFICATION MASTER R BYTE WITH R SIGNAL AT SDA SIGNALS FROM C THE SLAVE K FIGURE 18. RANDOM ADDRESS READ SEQUENCE 13 ISL21400 DATA DATA DATA STABLE CHANGE STABLE 1 HIGH WRITE IDENTIFICATION ADDRESS BYTE ...
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... Load capacitance up to 5000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21400 is not designed to drive heavily capacitive loads. For high impedance loads, an R-C network can be added to filter high frequency noise and preserve DC control ...
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... V OUT Typical Applications Circuits LDMOS RF Power Amplifier (RFPA). The ISL21400 is used to set the gate bias for the LDMOS transistor in a single stage of an RFPA. Normally this is done with a DAC or digital potentiometer with some discrete temperature compensation circuitry. The ISL21400 simplifies this control and allows a full range of DC bias and tempco control ...
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... OUT 2 GND +5V REGULATOR VCC C BUS SCL 6 SDA VOUT GND A2 ISL21400 FIGURE 19. LDMOS RFPA BIAS CONTROL 16 ISL21400 100 C1 100pF C2 RF INPUT +28V L1 RF OUTPUT Q1 LDMOS FN8091.0 December 14, 2006 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 ISL21400 M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE SYMBOL ...