ISL6173 Intersil Corporation, ISL6173 Datasheet - Page 3

• Manufacturer Part Number: ISL6173
• Description: Dual Low Voltage Hot Swap Controller
• Manufacturer: Intersil Corporation

Pinout
Pin Descriptions
PIN
10
1
2
3
4
5
6
7
8
9
NAME
PGND
SNS1
LTCH
FLT1
RTR/
GND
VO1
PG1
SS1
GT1
CT1
Current Sense Input
Soft-Start Duration Set
Input
Gate Drive Output
Fault Output
Power Good Output
Timer Capacitor
Retry Or Latch Input
Chip Gnd
Output Voltage 1
FUNCTION
3
SNS1
FLT1
VO1
PG1
SS1
GT1
CT1
This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.
This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for SS control.
A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
This is an open drain output. It asserts (pulls low) once the current regulation duration (determined
by the CTx timeout cap) has expired. This output is valid for Vbias>1V.
This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
A capacitor from this pin to ground controls the current regulation duration from the onset of current
regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches
V
The duration of current limit time-out = (C
When the OC comparator trips AND the RTR/LTCH pin is pulled low, the IC’s faulty channel remains
shut down for 64 cycles (each cycle length is equal to the current limit time-out duration).
This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left
floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after
an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for
64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.
This pin is also internally shorted to the metal tab at the bottom of the IC.
Charge pump ground. Both GND and PGND must be tied together externally.
CT_Vth
1
2
3
4
5
6
7
the GATE output is pulled down and the FLT is asserted.
28
8
27
9
28 LEAD QFN
ISL6173
TOP VIEW
10
26
11
25
12
24
13
23
TIM
DESCRIPTION
22
14
*1.178)/10µA
21
20
19
18
17
16
15
SNS2
VO2
SS2
GT2
FLT2
PG2
CT2
January 3, 2006
FN9186.3