ISL6327 Intersil Corporation, ISL6327 Datasheet - Page 19

• Manufacturer Part Number: ISL6327
• Description: Enhanced 6-Phase PWM Controller
• Manufacturer: Intersil Corporation

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Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of the normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during the regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
R
above in Output-Voltage Offset Programming. The selection
of C
and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T
R
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
C
REF
REF
REF
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
REF
is based on the desired offset voltage as detailed
and C
R
REF
is based on the time duration for 1 bit VID change
1.6V
VID
REF
=
, the relationship between the time constant of
VCC
+
-
REF
T
VID
network and T
0.4V
and C
E/A
GND
+
-
REF
FB
19
, can be used. The selection of
VID
is given by Equation 13.
DYNAMIC
VID D/A
ISL6327
OFS
DAC
VCC
GND
OR
(EQ. 13)
REF
R
R
REF
OFS
ISL6327
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6327 is
released from shutdown mode.
When all conditions above are satisfied, ISL6327 begins the
soft-start and ramps the output voltage to 1.1V first. After
1. The bias voltage applied at VCC must reach the internal
2. The ISL6327 features an enable input (EN_PWR) for
3. The voltage on EN_VTT must be higher than 0.875V to
FIGURE 7. POWER SEQUENCING USING THRESHOLD-
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6327 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6327 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6327 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6327 becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6327 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
FAULT LOGIC
CIRCUIT
SOFT-START
POR
AND
ISL6327 INTERNAL CIRCUIT
SENSITIVE ENABLE (EN) FUNCTION
COMPARATOR
ENABLE
+
-
0.875V
+
-
0.875V
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
10kΩ
910Ω
+12V
June 5, 2006
FN9276.1