ISL6523A Intersil Corporation, ISL6523A Datasheet - Page 8

• Manufacturer Part Number: ISL6523A
• Description: VRM8.5 Dual PWM and Dual Linear Power System Controller
• Manufacturer: Intersil Corporation

and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C
signals). An under-voltage on either linear output (VSEN3 or
VSEN4) is ignored until the respective UP signal goes high.
This allows V
start-up. Following an overcurrent event (OC1, OC2, or UV3
event), bringing the SS24 pin below 0.8V resets the
overcurrent latch and generates a soft-started ramp-up of
the outputs 1, 2, and 3.
OUT1 Overvoltage Protection
During operation, a short across the synchronous PWM
upper MOSFET (Q1) causes V
output exceeds the over-voltage threshold of 120% of
DACOUT, the over-voltage comparator trips to set the fault
latch and turns the lower MOSFET (Q2) on as needed to
regulate the output voltage to the 120% threshold. This
operation typically results in the blow of the input fuse,
subsequent discharge of V
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 7 illustrates the overcurrent protection with an overload
on OUT2. The overload is applied at T0 and the current
increases through the inductor (L
comparator trips when the voltage across Q3 (i
exceeds the level programmed by R
outputs 1, 2, and 3, discharges soft-start capacitor C
28 A current sink, and increments the counter. Soft-start
capacitor C
and initiates a soft-start cycle with the error amplifiers clamped
by soft-start. With OUT2 still overloaded, the inductor current
increases to trip the overcurrent comparator. Again, this
inhibits the outputs, but the soft-start voltage continues
increasing to above 4.0V before discharging. The counter
increments to 2. The soft-start cycle repeats at T3 and trips
the overcurrent comparator. The SS pin voltage increases to
above 4.0V at T4 and the counter increments to 3. This sets
the fault latch to disable the converter.
The PWM1 controller operates in the same way as PWM2 to
overcurrent faults. Additionally, the two linear controllers
monitor the VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the linear
under-voltage threshold, the respective UV signals set the
SS13
DS(ON)
SS
OUT3
pins are fully charged to above 4.0V (UP
is quickly discharged. C
and V
to monitor the current for protection
OUT4
OUT1
8
OUT1
to increase without fault at
.
OUT2
OCSET
to increase. When the
). At time T1, the OC2
SS24
. This inhibits
recharges at T2
D
•
r
DS(ON)
SS24
with
)
ISL6523A
OC latch or the FAULT latch, providing respective C
capacitors are fully charged. Blanking the UV signals during the
C
the under-voltage threshold during normal operation. Cycling
the bias input power off then on resets the counter and the
fault latch.
Resistors (R
trip levels for each PWM converter. As shown in Figure 8, the
internal 200 A current sink (I
R
enables the overcurrent comparator (OVERCURRENT1 or
OVERCURRENT2). When the voltage across the upper
MOSFET (V
comparator trips to set the overcurrent latch. Both V
V
R
MOSFET switching. The overcurrent function will trip at a peak
inductor current (I
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
DS
SS
OCSET
OCSET
where I is the output inductor ripple current.
are referenced to V
charge interval allows the linear outputs to build above
0A
4V
2V
0V
=
0
1
I
--------------------------------------------------- -
(V
helps V
OCSET
FIGURE 7. OVERCURRENT OPERATION
SET
OCSET1
DS(ON)
T0
COUNT
r
DS ON
= 1
OVERLOAD
) that is referenced to V
T1
APPLIED
PEAK
OCSET
PEAK)
R
) exceeds V
DS(ON)
OCSET
OCSET
and R
for I
IN
determined by:
track the variations of V
T2
and a small capacitor across
OCSET2
PEAK
at the highest junction temperature
from the specification table
OCSET
COUNT
SET
TIME
= 2
DISABLED
> I
) program the overcurrent
) develops a voltage across
, the overcurrent
CHIP
OUT(MAX)
IN
. The DRIVE signal
T3
+ ( I)/ 2,
IN
COUNT
= 3
due to
T4
SET
SS
and