ISL6534 Intersil Corporation, ISL6534 Datasheet
ISL6534
Available stocks
Related parts for ISL6534
ISL6534 Summary of contents
Page 1
... Dual PWM with Linear The ISL6534 is a versatile triple regulator that has two independent synchronous-rectified buck controllers with integrated 12V gate drivers (OUT1 and OUT2) and a linear controller (OUT3) to offer precision regulation three voltage rails. An optional shunt regulator allows 12V only operation, when a 5V supply is not available ...
Page 2
... SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020C. Add “-T” suffix for tape and reel. Pinouts (see Pin Descriptions, page 9) ISL6534 PKG. DWG. PACKAGE # M24.173B M24.173B L32.5x5 L32 ...
Page 3
... SS1/EN1 VCC5 30 µA www.DataSheet4U.com SS2/EN2 VCC5 30 µA SS3/EN3 3.3V PGOOD COMP1 FB1 0.6V REFIN FB2 COMP2 GND ISL6534 VCC POWER ON RESET AND CONTROL BIAS CURRENT 0.6V PGOOD = all 3 SS ramps done with no COMP short 3.3V 1-2 CLOCK CYCLE FILTER MONITOR IF SHORT > FILTER, COMP PINS SHUT DOWN ALL ...
Page 4
... VOUT1 (DDR) VTTREF VREF NOTE: Not all components are necessary in all applications. ISL6534 ISL6534 DDR MODE VCC VCC COMP1 FB1 COMP2 FB2 ISL6534 REFIN VCC REFOUT VREF PGOOD FS/SYNC SS1/EN1 DDR SS2/EN2 SS3/EN3 GND FIGURE 2. TYPICAL APPLICATION, DDRAM CONTROLLER 4 VOLTAGE OUTPUTS ...
Page 5
... VOUT1 VOUT2 VREF (IND) VTTREF VREF NOTE: Not all components are necessary in all applications. ISL6534 ISL6534 INDEPENDENT VCC VCC COMP1 FB1 COMP2 FB2 ISL6534 REFIN VCC REFOUT VREF PGOOD FS/SYNC SS1/EN1 SS2/EN2 IND SS3/EN3 GND FIGURE 3. TYPICAL APPLICATION, INDEPENDENT MODE 5 MODE ...
Page 6
... Output 2 Reference Voltage Outputs 1 and 2 System Accuracy Output 3 System Accuracy OSCILLATOR Accuracy Frequency ISL6534 Thermal Information Thermal Resistance Maximum Power Dissipation ___W Maximum Junction Temperature (Hermetic Package or Die 175°C Maximum Junction Temperature (Plastic Package 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s 300° ...
Page 7
... Source Current Sink Current Output Capacitance Output High Voltage Minimum ENABLE/SOFTSTART (SS/ Enable Threshold Noise Immunity (noise de-glitch) Soft-Start Current ISL6534 Operating Conditions 5V 12V CC12 TEST CONDITIONS FS_SYNC pin: resistor to GND; see Figure 12 for curves RL = 10kΩ to ground; (Note 100pF 10kΩ ...
Page 8
... UGATE Fall Time UGATE Rise Time UGATE Fall Time LGATE Rise Time LGATE Fall Time NOTES: 3. Operating range is: 12V ±10%; 5V ±10%. 4. Thermal comments. 5. Guaranteed by design. ISL6534 Operating Conditions 5V 12V CC12 TEST CONDITIONS End of ramp To select DDR mode; see Table 1 Use a 10K series resistor (from LG pin of another IC, for example) Voltage with respect to GND ...
Page 9
... The QFN package has two power pins; one for each switcher. They are electrically connected internally, but allow for separate decoupling caps to better isolate the switching noise, if necessary. Even if they share one capacitor, they should both be connected externally, for lower resistance. ISL6534 24 VCC 23 BOOT1 ...
Page 10
... GND is recommended for stability (see Application Considerations). DRIVE3 This pin drives the gate of an external N-Channel MOSFET, for OUT3, which is a linear regulator. ISL6534 10 PGOOD This digital output is an open-drain pull-down device. When power is first applied to the IC, the output is pulled low, for power “ ...
Page 11
... FB and the internal reference are the two inputs to the error amplifier, which are forced to be equal. The output voltage is externally divided down to the FB pin, to equal the reference. In the ISL6534, VOUT1 uses an internal 0.6V reference; VOUT2 uses an external REFIN pin for the reference. There are many variations of the above, especially when the modes (Independent or DDR) are also considered ...
Page 12
... Three resistors are needed; this is the most typical case. Case 3 can be used only when VOUT2 is greater than VREF, which is brought directly into REFIN; then VOUT2 is divided down to match it. Only two resistors (R1, R2) are needed, and both affect the accuracy. ISL6534 COMP1 FB1 EA R6 ...
Page 13
... SS1 SS2 FIGURE 7. CONNECTIONS FOR INDEPENDENT ENABLE AND SOFT-START OPEN-DRAIN LOGIC SIGNALS EN1, 2 EN3 C SS1 FIGURE 8. 1 AND 2 ENABLED TOGETHER BUT HAVE INDEPENDENT SOFT-STARTS FULLY INDEPENDENT. ISL6534 , and Figure 8, two SS2 SS3 SS1/EN1 SS2/EN2 SS3/EN3 C SS3 SS1/EN1 SS2/EN2 SS3/EN3 ...
Page 14
... Shunt Regulator The ISL6534 must have both a 12V (for VCC12) and a 5V power supply (for VCC); both must be above their respective POR rising trip points to enable the outputs to start switching. The shunt regulator (nominal 5.8V) was designed for those systems that do not have a 5V supply available ...
Page 15
... ISL6534 will go back to its default internal frequency. Note: Do not use the oscillator of another regulator directly, since the ISL6534 will scale match its own internal oscillator; using the LGATE signal will allow the ISL6534 to match its LGATE to the same frequency ...
Page 16
... DDR mode, where if VOUT1 is divided down for REFIN); it could be left open, but the additional noise and current draw may be objectionable. So even then, a capacitor is recommended. ISL6534 16 The REFOUT output is similar; a 0.1µF capacitor is recommended. If the output is not used, it could be left open, but the additional noise and current draw may be objectionable ...
Page 17
... The compensation network consists of the error amplifier (internal to the ISL6534) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin ...
Page 18
... FETs can be paralleled for higher currents; this spreads the heat between the FETs, which helps keep the temperature lower. However, the gate driver is now driving twice the gate capacitance, so there will be more dissipation in the ISL6534 gate drivers. Typical values for maximum current (based on 8-pin SOIC FETs surface-mounted on PCB, with no heatsinks or airflow) are 5A for a dual FET ...
Page 19
... Standard-gate MOSFETs (typically 30V breakdown and 20V maximum gate voltage) are normally recommended for use www.DataSheet4U.com with the ISL6534, especially since 12V is expected to be available to drive the gates. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFETs absolute gate-to-source voltage rating determine whether logic-level MOSFETs are appropriate ...
Page 20
... Note that the PHASE node is not brought into the ISL6534, so there is no way to reference the gate voltage to it often done in other regulators. The considerations for the BOOT2 pin are identical to BOOT1; but since they may have different VIN, VOUT, FETs, etc., the preferred solution for each output may be different for any given system ...
Page 21
... These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. ISL6534 21 Snubbers A snubber network is a series resistor and capacitor, usually from the phase node to GND (across the lower FET used to dampen the ringing of the phase node, which can introduce noise into other parts of the circuit ...
Page 22
... But it is important for the user to understand the method used, and the limitations of that method. There are no sense pins available on the ISL6534. This means that the many standard ways of sensing output current (sense resistors, FET r are not possible, without adding a lot of external components ...
Page 23
... Locate the ISL6534 within 1-2 inches (or even less, if possible) of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6534 must be sized to handle up to 1.5A peak current. Figure 22 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown ...
Page 24
... SS FIGURE 22. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES www.DataSheet4U.com Layout Considerations for the ISL6534 The metal plate on the bottom of either the TSSOP or QFN (MLFP) package must be soldered down to the PC board, and sufficient plane area given for heat transfer. The plane should be connected to GND (pin 15 in TSSOP); but left floating, it should NOT be tied to any other potential ...
Page 25
... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) www.DataSheet4U.com ISL6534 25 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL MIN NOMINAL A 0.80 0. 0.20 REF b 0.18 0.23 D 5.00 BSC D1 4.75 BSC D2 2.95 3.10 E 5.00 BSC E1 4.75 BSC E2 2.95 3.10 e 0.50 BSC k 0. 0.30 0.40 L1 ...
Page 26
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com ISL6534 0.25(0.010) M ...