ISL6537A Intersil Corporation, ISL6537A Datasheet - Page 11

• Manufacturer Part Number: ISL6537A
• Description: ACPI Regulator/Controller
• Manufacturer: Intersil Corporation

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FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
12V
KEY
ATX
GND PAD
ISL6537A
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
P12V
VDDQ(2)
COMP4
DRIVE2
DRIVE3
PHASE
LGATE
5VSBY
UGATE
AND ISLANDS
PWM4
VTT(2)
COMP
GNDP
FB4
FB2
FB3
FB
C
OUT2
R
R
C
C
C
C
2
6
R
2
BP
6
BP
R
10
5VSBY
12
R
R
11
4
8
R
R
C
C
11
9
1
5
C
C
3
7
R
R
5VDUAL
V
Q
1
Q
5
3.3VATX
TT
R
R
1
2
3
7
C
OUT5
Q
L
3
C
1
C
C
IN
3.3VATX
OUT1
V
OUT3
DDQ
V
Q
DAC
Q
Q
V
C
3
1
TT_GMCH/CPU
2
OUT4
V
DDQ
V
C
GMCH
IN
L
2
ISL6537A
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converters
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier output (V
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V
∆V
OUT
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
OSC
V
) is regulated to the Reference voltage level. The error
DDQ
OSC
COMPARATOR
OUT
=
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
V
0.8
ISL6537A
E/A
PWM
/V
E/A
×
Z
+
E/A
-



FB
-
+
COMP
LC
1
) is compared with the oscillator (OSC)
C
+
. This function is dominated by a DC
REFERENCE
2
REFERENCE
and a zero at F
R
------ -
R
C
1
4
-
+
1



O
IN
DRIVER
DRIVER
R
and C
Z
2
IN
at the PHASE node. The
OSC
FB
O
Z
FB
), with a double pole
ESR
.
PHASE
R
(PARASITIC)
V
C
4
IN
3
IN
L
Z
R
. The DC Gain of
O
IN
1
) divided by the
O
R
ESR
C
3
and C
O
V
DDQ
V
FN9143.3
O
DDQ
).