ISL6552 Intersil Corporation, ISL6552 Datasheet - Page 13

• Manufacturer Part Number: ISL6552
• Description: Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

controller is under full load. This droop compensation allows
larger transient voltage deviations and thus reduces the size
and cost of the output filter components.
R
the normal full load current 50µA applied through the R
resistor (or at a different full load current if adjusted as
outlined in the Over-Current, Selecting R
R
For a Vdroop of 80mV, R
The AC feedback components, R
relation to R
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of all
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
r
r
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (I
and a sawtooth current, (i
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
i
Where:
Example: For V
Then i
The inductor, or load current, flows alternately from V
through Q1 and from ground through Q2. The ISL6552
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, i/F
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
PK-PK
DS(ON)
DS(ON)
IN
IN
should be selected to give the desired “droop” voltage at
= Vdroop/50µA
PK-PK
= (V
, the current through that phase will be reduced.
between synchronous rectifiers. If a FET has a higher
V
IN
CORE
IN
F
F
= 4.3A
V
V
.
SW
SW
x V
IN
IN
CORE
L = value of the inductor
L = 1.3µH,
CORE
= 12V,
= DC value of the output or V
= DC value of the input or supply voltage
= switching frequency
= 250kHz,
= 1.6V,
- V
IN
PK-PK
CORE
= 1.6kΩ
13
) resulting from switching.
2
FB
)/(L x F
and Cc, are scaled in
ISEN
SW
SW
x V
section).
ID
, after Q1 is
IN
voltage
LT
)
IN
/ n),
ISEN
ISL6552
average current per phase. Neglecting secondary effects,
the sampled current (I
current (I
I
Where:
Example: Using the previously given conditions, and
For
Then
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is
r
PHASE node, is applied through the R
ISL6552 ISEN pin. This pin is held at virtual ground, so the
current into ISEN is:
I
R
SAMPLE
SENSE
DSON
Isen
FIGURE 8. TWO CHANNEL MULTI-PHASE SYSTEM WITH
FIGURE 9. TWO CHANNEL MULTI-PHASE SYSTEM WITH
25
20
15
10
5
0
= I
25
20
15
10
(Q2) x I
= I
5
0
I
SAMPLE
LT
= I
SAMPLE
SAMPLE
) by:
LT
CURRENT BALANCING DISABLED
CURRENT BALANCING ENABLED
/ n + (V
I
I
LT
LT
SAMPLE
n = the number of channels
n = 4
x r
= 100A,
= total load current
= 25.49A
x r
DS(ON)
IN
SAMPLE
DS(ON)
V
. The voltage at Q2’s drain, the
CORE
(Q2)/50µA
(Q2)/R
) can be related to the load
-3V
CORE
ISEN
ISEN
2
)/(6L x F
.
resistor to the
SW
x V
IN
)