ISL6559 Intersil Corporation, ISL6559 Datasheet - Page 17

• Manufacturer Part Number: ISL6559
• Description: Multi-Phase PWM Controller
• Manufacturer: Intersil Corporation

In Equations 24, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V
the peak-to-peak sawtooth signal amplitude as described in
Figure 4 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy during the interval of time after
the beginning of the transient until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response leaving the output capacitor bank
to supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
∆V
≈
(
ESL
)
di
---- -
dt
MAX
+
(
MAX
. Capacitors are characterized according to
ESR
.
) ∆I
17
(EQ. 25)
PP
is
ISL6559
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I
are selected, the maximum allowable ripple voltage,
V
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆V
Equation 28 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 27
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L
L
L
PP(MAX)
≤
≤
≥
MAX
2NCV
-------------------- - ∆V
(
------------------------- - ∆V
(
1.25
(
ESR
∆I
(
∆I
. This places an upper limits on inductance.
)
2
) NC
)
O
2
)
, determines the lower limit on the inductance.


----------------------------------------------------------- -
V
IN
f
S
C,PP
MAX
V
–
MAX
IN
N V
V
–
(ESR). Thus, once the output capacitors
OUT
PP MAX
∆I ESR
–
∆I ESR
(
(
 V

(
OUT
)
)
)


V
IN
–
V
O


(EQ. 26)
(EQ. 27)
(EQ. 28)