ISL6567 Intersil Corporation, ISL6567 Datasheet - Page 20

• Manufacturer Part Number: ISL6567
• Description: Multipurpose Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
G
G
G
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
4. Calculate R3 such that F
2. Calculate C1 such that F
3. Calculate C2 such that F
MOD
FB
CL
value for R2 for desired converter bandwidth (F
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 24, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier, in order to compensate for the
attenuation introduced by the resistor divider, the
obtained R2 value needs be multiplied by a factor of
(R
unchanged, as long as the compensated R2 value is
used.
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R3
R2
C1
C2
f ( )
f ( )
P
f ( )
+R
=
=
=
=
=
=
⋅
=
----------------------------------------------------- - ⋅
s f ( ) R1
---------------------------------------------------------------------------------------------------------------------------- -
(
--------------------- -
F
----------- - 1
G
-------------------------------------------- -
d
----------------------------------------------- -
2π R2 0.5 F
---------------------------------------------------------
2π R2 C1 F
F
S
1
V
MAX
SW
SW
1
LC
MOD
d
----------------------------- -
)/R
+
OSC
R1
⋅
⋅
MAX
+
⋅
s f ( ) R3 C3
V
P2
). F
s f ( ) R2 C1
P
–
OSC
⋅
. The remainder of the calculations remain
f ( ) G
V
⋅
FB
⋅
⋅
⋅
1
is placed below F
⋅
SW
⋅
R1 F
IN
C1
V
⋅
⋅
(
) and closed-loop response (G
C1
IN
1
⋅
LC
⋅
⋅
FB
⋅
+
F
represents the per-channel switching
⋅
⋅
⋅
+
LC
s f ( )
----------------------------------------------------------------------------------------
1
0
(to adjust, change the 0.5 factor to
LC
CE
f ( )
C2
+
)
s f ( )
Z1
–
⋅
⋅
P1
Z2
)
(
⎛
⎝
1
20
R1
1
C3
is placed at a fraction of the F
is placed at F
is placed at F
⋅
+
(
1
+
s f ( ) R2
E
=
where s f ( )
+
R3
SW
+
CE
-------------------------------------------------
2π R3 0.7 F
s f ( ) E C
D
⋅
) C3
) C
/F
⋅
(typically, 0.5 to 1.0
⋅
⋅
⋅
,
LC
MOD
⋅
⎛
⎝
+
, the lower the F
⋅
⋅
--------------------- -
C1
P2
C1 C2
CE
LC
LC
1
s
2
), feedback
=
f ( ) L C
).
. Calculate C3
lower in
+
.
⋅
⋅
2π f j
C2
⋅
SW
⎞
⎠
⋅ ⋅
CL
⋅
⎞
⎠
0
). If
):
LC
Z1
ISL6567
,
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 25 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 25 by adding the modulator gain,
G
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model presented
makes a number of approximations and is generally not
accurate at frequencies approaching or exceeding half the
switching frequency. When designing compensation networks,
select target crossover frequencies in the range of 10% to 30%
of the per-channel switching frequency, F
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
capacitor bank to supply the load current or sink the inductor
F
FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z2
MOD
F
0
Z1
=
LOG
(in dB), to the feedback compensation gain, G
-------------------------------------------------- -
2π
20
=
log
⋅
------------------------------- -
2π R2 C1
(
R1
⎛
⎝
R2
------- -
R1
⋅
1
+
1
⎞
⎠
R3
⋅
F
) C3
Z1
⋅
F
F
LC
P2
Z2
against the capabilities of the error
F
F
F
CE
P1
P1
F
P2
=
CL
F
0
---------------------------------------------- -
2π R2
F
=
, is constructed on the
20
P2
------------------------------- -
2π R3 C3
⋅
log
G
SW
CL
⋅
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
⋅
CLOSED LOOP GAIN
MAX V
G
1
1
.
V
--------------------- -
C1
MODULATOR GAIN
MOD
C1 C2
OSC
⋅
FREQUENCY
+
⋅
⋅
C2
IN
March 20, 2007
G
FB
FB
FN9243.2
(in