ISL6569A Intersil Corporation, ISL6569A Datasheet
ISL6569A
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ISL6569A Summary of contents
Page 1
... Data Sheet Multi-Phase PWM Controller The ISL6569A provides core-voltage regulation by driving two interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output ripple currents. The reduction in ripple results in lower component cost, reduced dissipation, and a smaller implementation area ...
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... IOUT 12 13 VDIFF 2 ISL6569A EN FS/DIS PGOOD ISEN1 PWM1 VID2 PWM2 VID1 GND ISEN2 VID0 VCC GND RGND OFS VSEN COMP ISL6569ACR (32 LD 5x5 QFN) TOP VIEW ...
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... Block Diagram VID4 VID3 DYNAMIC VID2 VID DAC VID1 VID0 e/a FB COMP OFS x0.1 100µA VDIFF 2.2V VSEN diff RGND AVERAGE IDROOP 3 ISL6569A PGOOD VCC EN 6V POR AND SOFT START 90µ 1/2 + GND FS 1.23V OSCILLAT0R AND SAWTOOTH I1 CURRENT SENSE I2 PWM1 PWM2 OVP ISEN1 ...
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... VCC VDIFF PWM1 FB IOUT ISEN1 COMP ISL6569A OFS FS/DIS VID4 VID3 VID2 VID1 PWM2 VID0 PGOOD ISEN2 +12V EN GND 4 ISL6569A +12V 300Ω PVCC BOOT UGATE VCC PHASE DRIVER HIP6601B LGATE PWM GND +12V PVCC BOOT UGATE VCC R T PHASE DRIVER ...
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... VID Input Low Level VID Input High Level PIN-ADJUSTABLE OFFSET OFS Current Offset Accuracy OSCILLATOR Accuracy Adjustment Range 5 ISL6569A Thermal Information Thermal Resistance (Typical, Note 1) + 0.3V SOIC Package (Note QFN Package (Notes 2, 3 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . -65 Maximum Lead Temperature ...
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... Over-Current Trip Level POWER GOOD AND PROTECTION MONITORS PGOOD Low Voltage Under-Voltage Offset From VID Over-Voltage Threshold OVP Voltage NOTE: 4. These parts are designed and adjusted for accuracy within the system tolerance. 6 ISL6569A Unless Otherwise Specified. (Continued) A TEST CONDITIONS I ...
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... If droop is effective and thermally viable have forced a change to the DS(ON) cost-saving approach of multi-phase. The ISL6569A controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagram in Figure 1 provides a top level view of multi-phase power conversion using the ...
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... VDIFF VSEN RGND FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF A ISL6569A CONVERTER Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with the other channel 2-phase converter, channel-2 switches half a cycle after channel- result, the converter has a ripple frequency twice that of either phase ...
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... Figure 16 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle provided as an aid in determining the optimal input capacitor solution. 9 ISL6569A INPUT-CAPACITOR CURRENT, 10A/DIV (EQ. 1) CHANNEL 2 CHANNEL 2 INPUT CURRENT INPUT CURRENT ...
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... During the forced off time following a PWM transition low, the controller senses channel load current by sampling the voltage across the lower MOSFET ground-referenced DS(ON) amplifier, internal to the ISL6569A, connects to the PHASE node through a resistor The voltage across R ISEN equivalent to the voltage drop across the r MOSFET while it is conducting ...
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... DAC) plus offset errors in the OFS current source, remote- V COMP + sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6569A to include all variations in current sources, amplifiers and the reference so that the output voltage remains within the specified system tolerance of ±0.5% over temperature. VID4 ...
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... Shutdown The ISL6569A checks the five VID inputs at the beginning of each channel-1 switching cycle. If the VID code has changed, the controller waits one complete switching cycle to validate the new code. If the VID code is stable for this entire switching cycle, then the controller will begin executing the output voltage change ...
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... Second, the ISL6569A features an enable input (EN) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6569A in shutdown until the voltage at EN rises above 1.23V. The enable comparator has about 90mV of hysteresis to prevent bounce important that the driver ICs reach their POR level before the ISL6569A becomes enabled ...
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... Over-Voltage Protection When the output of the differential amplifier (VDIFF) reaches 2.2V, PGOOD immediately goes low indicating a fault. Two protective actions are taken by the ISL6569A to protect the microprocessor load. First, all PWM outputs are commanded low. Directing the Intersil drivers to turn on the lower MOSFETs; shunting the output to ground preventing any further increase in output voltage ...
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... MOSFET or SCR will not overheat before the fuse blows. Once an over-voltage condition is detected, normal PWM operation ceases and PGOOD remains low until the ISL6569A is reset. Cycling the voltage on EN below 1.23V or the bias to VCC below the POR-falling threshold will reset the controller. ...
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... A third component involves the lower MOSFET’s reverse- recovery charge Since the inductor current has fully rr commutated to the upper MOSFET before the lower- MOSFET’s body diode can draw all ISL6569A /V ); and through the upper MOSFET across VIN. The power OUT IN dissipated as a result is P ...
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... ESL ---- - + ESR dt 17 ISL6569A The filter capacitor must have sufficiently low ESL and ESR so that ∆V < ∆V in Figure 6. FB Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance, but limited high-frequency performance ...
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... V DROOP - VDIFF FIGURE 13. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6569A CIRCUIT In Equations 27 the per-channel filter inductance divided by 2 (the number of active channels the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and V the peak-to-peak sawtooth signal amplitude as described in Figure 6 and Electrical Specifications ...
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... Figure 6 and Electrical Specifications. Input Supply Voltage Selection The VCC input of the ISL6569A can be connected to either a +5V supply directly or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300Ω ...
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... The ISL6569A can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 21 ISL6569A M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 ISL6569A L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...